SMJ44400 Datasheet, PDF (3/21 Pages) Austin Semiconductor – 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY

DRAM
SMJ44400
Power Up (continued)
required after full Vcc level is achieved. These eight initializa-
tion cycles need to include at least one refresh (RAS\-only or
CBR) cycle.
Test Mode
An industry standard Design For Test (DFT) mode is
incorporated in the SMJ44400. A CBR with W\ low (WCBR)
cycle is used to enter test mode. In the test mode, data is written
into and read from eight sections of the array in parallel.
All data is written into the array through DQ1. Data is com-
parted upon reading and if all bits are equal, all DQ pins go
high. If any one bit is different, all the DQ pins go low. Any
combination read, write, read-write, or page-mode can be used
in the test mode. The test mode function reduces test times by
enabling the 1M x 4-bit DRAM to be tested as if it were a 512K
DRAM where column address 0 is not used. A RAS\-only or
CBR refresh cycle is used to exit the DFT mode.
LOGIC SYMBOL¹
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
6
7
8
9
11
12
13
14
15
5
RAS\ ⁴
CAS\ ¹⁷
W\
OE\
3
16
RAM 1024K x 4
20D10/21D0
A
0
1 048 575
20D19/21D9
C20[Row]
G23/[Refresh Row]
24[Power Down]
C21[Column]
G24
&
23C22
23,21D
G25
24,25EN
DQ1 ¹
DQ2
DQ3
DQ4
2
18
19
A, 22D
26
A, Z26
1. This symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12. The pinouts illustrated are for the JD package.
SMJ44400
Rev. 2.2 01/10
Micross Components reserves the right to change products or specifications without notice.
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