SMJ44400 Datasheet, PDF (14/21 Pages) Austin Semiconductor – 1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY

DRAM
SMJ44400
ENHANCED-PAGE-MODE READ-WRITE-CYCLE TIMING²
(1)
(1)
NOTES:
1. Valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an invalid-data state prior to the specified access times as the outputs are driven when
CAS\ and OE\ are low.
2. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
SMJ44400
Rev. 2.2 01/10
14
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