A2F500M3G-CSG288 Datasheet, PDF (30/197 Pages) Microsemi Corporation – SmartFusion Customizable System-on-Chip (cSoC)

SmartFusion DC and Switching Characteristics
Microcontroller Subsystem Dynamic Contribution—P_MSS
SoC Mode
P_MSS = P_AC22
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some
examples:
• The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the clock
frequency.
• The average toggle rate of an 8-bit counter is 25%:
– Bit 0 (LSB) = 100%
– Bit 1 = 50%
– Bit 2 = 25%
–…
– Bit 7 (MSB) = 0.78125%
– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
non-tristate output buffers are used, the enable rate should be 100%.
Table 2-17 • Toggle Rate Guidelines Recommended for Power Calculation
Component
α₁
α₂
Definition
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Guideline
10%
10%
Table 2-18 • Enable Rate Guidelines Recommended for Power Calculation
Component
Definition
β₁
I/O output buffer enable rate
Guideline
Toggle rate of the logic driving the
output buffer
β₂
FPGA fabric SRAM enable rate for read
operations
12.5%
β₃
FPGA fabric SRAM enable rate for write
operations
12.5%
β₄
eNVM enable rate for read operations
< 5%
2-18
Revision 12