A2F500M3G-CSG288 Datasheet, PDF (157/197 Pages) Microsemi Corporation – SmartFusion Customizable System-on-Chip (cSoC)

SmartFusion Customizable System-on-Chip (cSoC)
Pin
No.
A2F060 Function
FG256
A2F200 Function
A2F500 Function
A1
GND
GND
GND
A2
VCCFPGAIOB0
VCCFPGAIOB0
VCCFPGAIOB0
A3
EMC_AB[0]/IO04NDB0V0
EMC_AB[0]/IO04NDB0V0
EMC_AB[0]/IO06NDB0V0
A4
EMC_AB[1]/IO04PDB0V0
EMC_AB[1]/IO04PDB0V0
EMC_AB[1]/IO06PDB0V0
A5
GND
GND
GND
A6
EMC_AB[3]/IO05PDB0V0
EMC_AB[3]/IO05PDB0V0
EMC_AB[3]/IO09PDB0V0
A7
EMC_AB[5]/IO06PDB0V0
EMC_AB[5]/IO06PDB0V0
EMC_AB[5]/IO10PDB0V0
A8
VCCFPGAIOB0
VCCFPGAIOB0
VCCFPGAIOB0
A9
GND
GND
GND
A10 EMC_AB[14]/IO11NDB0V0
EMC_AB[14]/IO11NDB0V0
EMC_AB[14]/IO15NDB0V0
A11 EMC_AB[15]/IO11PDB0V0
EMC_AB[15]/IO11PDB0V0
EMC_AB[15]/IO15PDB0V0
A12
GND
GND
GND
A13 EMC_AB[20]/IO14NDB0V0
EMC_AB[20]/IO14NDB0V0
EMC_AB[20]/IO21NDB0V0
A14 EMC_AB[24]/IO16NDB0V0
EMC_AB[24]/IO16NDB0V0
EMC_AB[24]/IO20NDB0V0
A15
VCCFPGAIOB0
VCCFPGAIOB0
VCCFPGAIOB0
A16
GND
GND
GND
B1
EMC_DB[15]/IO45PDB5V0
EMC_DB[15]/GAA2/IO71PDB5V0 EMC_DB[15]/GAA2/IO88PDB5V0
B2
GND
GND
GND
B3 EMC_BYTEN[1]/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO02PDB0V0 EMC_BYTEN[1]/GAC1/IO07PDB0V0
B4 EMC_OEN0_N/IO03NDB0V0
EMC_OEN0_N/IO03NDB0V0
EMC_OEN0_N/IO08NDB0V0
B5 EMC_OEN1_N/IO03PDB0V0
EMC_OEN1_N/IO03PDB0V0
EMC_OEN1_N/IO08PDB0V0
B6
EMC_AB[2]/IO05NDB0V0
EMC_AB[2]/IO05NDB0V0
EMC_AB[2]/IO09NDB0V0
B7
EMC_AB[4]/IO06NDB0V0
EMC_AB[4]/IO06NDB0V0
EMC_AB[4]/IO10NDB0V0
B8
EMC_AB[9]/IO08PDB0V0
EMC_AB[9]/IO08PDB0V0
EMC_AB[9]/IO13PDB0V0
B9 EMC_AB[12]/IO10NDB0V0
EMC_AB[12]/IO10NDB0V0
EMC_AB[12]/IO14NDB0V0
B10 EMC_AB[13]/IO10PDB0V0
EMC_AB[13]/IO10PDB0V0
EMC_AB[13]/IO14PDB0V0
B11 EMC_AB[16]/IO12NDB0V0
EMC_AB[16]/IO12NDB0V0
EMC_AB[16]/IO17NDB0V0
B12 EMC_AB[18]/IO13NDB0V0
EMC_AB[18]/IO13NDB0V0
EMC_AB[18]/IO18NDB0V0
B13 EMC_AB[21]/IO14PDB0V0
EMC_AB[21]/IO14PDB0V0
EMC_AB[21]/IO21PDB0V0
B14 EMC_AB[25]/IO16PDB0V0
EMC_AB[25]/IO16PDB0V0
EMC_AB[25]/IO20PDB0V0
B15
GND
GND
GND
Notes:
1. Shading denotes pins that do not have completely identical functions from density to density. For example, the bank
assignment can be different for an I/O, or the function might be available only on a larger density device.
2. *: Indicates that the signal assigned to the pins as a CLKBUF/CLKBUF_LVPECL/CLKBUF_LVDS goes through a
glitchless mux. In order for the glitchless mux to operate correctly, the signal must be a free-running clock signal. Refer to
the ’Glitchless MUX’ section in the SmartFusion Microcontroller Subsystem User’s Guide for more details.
Revision 12
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