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A2F500M3G-CSG288 Datasheet, PDF (28/197 Pages) Microsemi Corporation – SmartFusion Customizable System-on-Chip (cSoC) | |||
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SmartFusion DC and Switching Characteristics
Standby Mode and Time Keeping Mode
PNET = 0 W
I/O Input Buffer Dynamic ContributionâPINPUTS
SoC Mode
PINPUTS = NINPUTS * (α2 / 2) * PAC9 * FCLK
Where:
NINPUTS is the number of I/O input buffers used in the design.
α2 is the I/O buffer toggle rateâguidelines are provided in Table 2-17 on page 2-18.
FCLK is the global clock signal frequency.
Standby Mode and Time Keeping Mode
PINPUTS = 0 W
I/O Output Buffer Dynamic ContributionâPOUTPUTS
SoC Mode
POUTPUTS = NOUTPUTS * (α2 / 2) * β1 * PAC10 * FCLK
Where:
NOUTPUTS is the number of I/O output buffers used in the design.
α2 is the I/O buffer toggle rateâguidelines are provided in Table 2-17 on page 2-18.
β1 is the I/O buffer enable rateâguidelines are provided in Table 2-18 on page 2-18.
FCLK is the global clock signal frequency.
Standby Mode and Time Keeping Mode
POUTPUTS = 0 W
FPGA Fabric SRAM Dynamic ContributionâPMEMORY
SoC Mode
β β PMEMORY = (NBLOCKS * PAC11 * 2 * FREAD-CLOCK) + (NBLOCKS * PAC12 * 3 * FWRITE-CLOCK)
Where:
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
β2 is the RAM enable rate for read operationsâguidelines are provided in Table 2-18 on
page 2-18.
β3 the RAM enable rate for write operationsâguidelines are provided in Table 2-18 on page 2-18.
FWRITE-CLOCK is the memory write clock frequency.
Standby Mode and Time Keeping Mode
PMEMORY = 0 W
PLL/CCC Dynamic ContributionâPPLL
SoC Mode
PPLL = PAC13 * FCLKOUT
FCLKIN is the input clock frequency.
FCLKOUT is the output clock frequency.1
Standby Mode and Time Keeping Mode
1.The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula output clock by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL
contribution.
2-16
Revision 12
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