A2F500M3G-CSG288 Datasheet, PDF (10/197 Pages) Microsemi Corporation – SmartFusion Customizable System-on-Chip (cSoC)

SmartFusion Family Overview
ProASIC3 FPGA Fabric
The SmartFusion cSoC family, based on the proven, low power, firm-error immune ProASIC^®3 flash
FPGA architecture, benefits from the advantages only flash-based devices offer:
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flash-
based SmartFusion cSoCs are Instant On and do not need to be loaded from an external boot PROM at
each power-up. On-board security mechanisms prevent access to the programming information and
enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system
programming (ISP) to support future design iterations and critical field upgrades, with confidence that
valuable IP cannot be compromised or copied. Secure ISP can be performed using the industry standard
AES algorithm with MAC data authentication on the device.
Low Power
Flash-based SmartFusion cSoCs exhibit power characteristics similar to those of an ASIC, making them
an ideal choice for power-sensitive applications. With SmartFusion cSoCs, there is no power-on current
and no high current transition, both of which are common with SRAM-based FPGAs.
SmartFusion cSoCs also have low dynamic power consumption and support very low power time-
keeping mode, offering further power savings.
Security
As the nonvolatile, flash-based SmartFusion cSoC family requires no boot PROM, there is no vulnerable
external bitstream. SmartFusion cSoCs incorporate FlashLock^®, which provides a unique combination of
reprogrammability and design security without external overhead, advantages that only a device with
nonvolatile flash programming can offer.
SmartFusion cSoCs utilize a 128-bit flash-based key lock and a separate AES key to provide security for
programmed IP and configuration data. The FlashROM data in Fusion devices can also be encrypted
prior to loading. Additionally, the flash memory blocks can be programmed during runtime using the AES-
128 block cipher encryption standard (FIPS Publication 192).
SmartFusion cSoCs with AES-based security are designed to provide protection for remote field updates
over public networks, such as the Internet, and help to ensure that valuable IP remains out of the hands
of system overbuilders, system cloners, and IP thieves. As an additional security measure, the FPGA
configuration data of a programmed Fusion device cannot be read back, although secure design
verification is possible. During design, the user controls and defines both internal and external access to
the flash memory blocks.
Security, built into the FPGA fabric, is an inherent component of the SmartFusion cSoC family. The flash
cells are located beneath seven metal layers, and many device design and layout techniques have been
used to make invasive attacks extremely difficult. SmartFusion cSoCs, with FlashLock and AES security,
are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is
protected with industry standard security measures, making remote ISP feasible. A SmartFusion cSoC
provides the highest security available for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based SmartFusion
cSoCs do not require system configuration components such as electrically erasable programmable
read-only memories (EEPROMs) or microcontrollers to load device configuration data during power-up.
This reduces bill-of-materials costs and PCB area, and increases system security and reliability.
Instant On
Flash-based SmartFusion cSoCs are Instant On. Instant On SmartFusion cSoCs greatly simplify total
system design and reduce total system cost by eliminating the need for complex programmable logic
devices (CPLDs). SmartFusion Instant On clocking (PLLs) replace off-chip clocking resources. In
addition, glitches and brownouts in system power will not corrupt the SmartFusion flash configuration.
Unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored.
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