DDP3300A Datasheet, PDF (39/53 Pages) Micronas – Single-Chip Display and Deflection Processor

PRELIMINARY DATA SHEET
DDP 3300 A
4.6.5. Bus Inputs: Luma, Chroma, OSD, Front Sync (see Fig. 4–17)
Symbol Parameter
V_IL
Input Low Voltage
V_IH
Input High Voltage
t_IS
Input Setup Time
t_IH
Input Hold Time
Pin Name Min.
Typ.
Max.
Unit
Y[0..7]
–
–
C[0..7]
OSD[0:4] 1.5
–
FSY
7
–
0.8
V
–
V
–
ns
–
–
6
ns
Test Conditions
Main Clock
Data Inputs
Y,C,RGB,Fsync
t_IS
t_IH
Fig. 4–17: Picture bus input timing
4.6.6. 20.25 MHz Main Clock Input, internally AC coupled (see Fig. 4–18)
Symbol
Parameter
Pin Name Min.
V_IT
Input Trigger Level
CLK20
2.1
f_Φ
Φ Main Clock Frequency
10
V_ΦMIDC Φ Main Clock Input DC Volt-
1.0
age
V_ΦMIAC Φ M Clock Input AC Voltage
0.8
(p–p)
t_ΦMIH
Φ M Clock Input High/Low
0.9
t_ΦMIL
Ratio
t_ΦMIHL
Φ M Clock Input High to Low
–
Transition Time
t_ΦMILH
Φ M Clock Input Low to High
–
Transition Time
Typ.
2.5
20.25
–
Max.
2.9
24
3.5
Unit
V
MHz
V
Test Conditions
–
2.5
V
1.0
1.1
–
0.15
f_ΦM
–
0.15
f_ΦM
t_ΦMILH
t_ΦMIHL
V_ΦMIAC
Fig. 4–18: Main clock input
t_ΦMIH
t_ΦMIL
V_ΦMIDC
0V
DVSS
MICRONAS INTERMETALL
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