DDP3300A Datasheet, PDF (18/53 Pages) Micronas – Single-Chip Display and Deflection Processor

DDP 3300 A
PRELIMINARY DATA SHEET
MSY
FSY
main
sync
generator
PLL3
skew
measure–
ment
phase
comparator
&
lowpass
DCO
blanking, clamping, etc.
sinewave
generator
DAC
&
LPF
Standby clock
1:64
&
output
stage
front
sync
interface
display
timing
phase
comparator
&
lowpass
DCO
vertical reset
PLL2
line
counter
composite
sync
generator
clock & control
H
flyback
H
drive
CSY
V
flyback
VDATA
vertical
serial
data
Fig. 2–16: Deflection processing block diagram
E/W
correction
PWM
15 bit
sawtooth
PWM
15 bit
E/W
ouput
V
output
input
analog
video
MSY ^{M1 M2}
(not in scale)
timing reference for PICTURE bus
– chroma multiplex sync
– active picture data after xxx clocks
Fig. 2–17: Main sync format
M1
line
[0]
line
[7]
Parity
M2
line _{not not not not not}
[8] _{used used used used used}
F
V Parity
V: Vert. blanking
0 = off
1 = on
F: Field #
0 = Field 1
1 = Field 2
line: Field line #
1...N
2.3.2. Horizontal Phase Adjustment
This section describes a simple way to align PLL phases
and the horizontal frame position.
1. The parameter NEWLIN in the VPC 320X has to be
adjusted. The minimum possible value is 34 (recom-
mended for a standard 4:3 signal).
2. With HDRV, the duration of the horizontal drive pulse
has to be adjusted.
18
3. With POFS2, the clamping pulse for the analog RGB
input has to be adjusted to the correct position, e.g.
the pedestal of the generator signal.
4. With POFS3, the horizontal position of the analog
RGB signal (from SCART) has to be adjusted.
5. With HPOS, the digital RGB output signal (from VPC)
has to be adjusted to the correct horizontal position.
6. With HBST and HBSO, the start and stop values for
the horizontal blanking have to be adjusted.
MICRONAS INTERMETALL