DDP3300A Datasheet, PDF (19/53 Pages) Micronas – Single-Chip Display and Deflection Processor

PRELIMINARY DATA SHEET
DDP 3300 A
2.3.3. Vertical and East/West Deflection
The calculations of the vertical and East/West deflection
waveforms are done in the video front-end, i.e., the
VPC 320X. The algorithm uses a chain of accumulators
to generate the required polynomial waveforms. To pro-
duce the deflection waveforms, the accumulators are
initialized at the beginning of each field. The initialization
values must be computed by the TV control processor
and are written to the VPC 320X once. The waveforms
are described as polynomials in x, where x varies from
0 to 1 for one field.
P: a + b(x–0.5) + c(x–0.5)² + d(x–0.5)³ + e(x–0.5)⁴
The initialization values for the accumulators a0..a3 for
vertical deflection and a0..a4 for East/West deflection
are 12-bit values.
The vertical waveform can be scaled according the
average beam current. This is used to compensate the
effects of electric high tension changes due to beam cur-
rent variations. In order to get a faster vertical retrace
timing, the output impedance of the vertical
D/A-converter can be reduced by 50% during the re-
trace.
Fig. 2–18 shows some vertical and East/West deflection
waveforms. The polynomial coefficients are also stated.
Detailed information on the programming of the vertical
and East/West deflection parameters is given in the
VPC 320X datasheet.
Fig. 2–18: Vertical and East/West Deflection Waveforms
Vertical: a,b,c,d 0,1,0,0
0,1,1,0
0,1,0,1
East/West: a,b,c,d,e
0,0,1,0,0
0,0,0,0,1
0,0,1,1,1
2.3.4. Protection Circuitry
– Picture tube and drive stage protection is provided
through the following measures:
– Vertical flyback protection input: this pin searches for
a negative edge in every field, otherwise the RGB
drive signals are blanked.
– Drive shutoff during flyback: this feature can be se-
lected by software.
– Safety input pin: this input has two thresholds. Be-
tween zero and the lower threshold, normal function-
ing takes place. Between the lower and the higher
threshold, the RGB signals are blanked. Above the
higher threshold, the RGB signals are blanked and the
horizontal drive is shut off. Both thresholds have a
small hysteresis.
– The main oscillator (not included in the DDP ) and the
horizontal drive circuitry are run from a separate
(standby) power supply and are already active while
the TV set is powering up.
2.3.5. Deflection Bus
The deflection bus is a serial, bidirectional interface be-
tween the DDP and the Fast Processor in the VPC chip,
so the calculation of the vertical and the East/West sig-
nals is performed by the FP in the VPC. The FP in the
VPC also does the beam current limitation. The follow-
ing data is transferred via the deflection bus:
– vertical and East/West drive values for the VERT and
EW DAC from VPC to DDP
– values for R/G/B DACs for ext. brightness, internal
brightness, external contrast, white drive from VPC to
DDP
– tube current measurement from DDP to VPC
– status bits from DDP to VPC
– vertical reset of deflection back-end (from VPC to
DDP).
MICRONAS INTERMETALL
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