DDP3300A Datasheet, PDF (20/53 Pages) Micronas – Single-Chip Display and Deflection Processor

DDP 3300 A
PRELIMINARY DATA SHEET
2.4. Reset and Standby Functions
Reset of most functions (exceptions see below) is per-
formed by a reset pin. When this pin becomes active, all
the internal registers and counters are set to zero. When
this pin is released, the internal reset is still active for
approximately 4 µs. After that time all the internal regis-
ters are loaded with the values defined in the defaults
ROM. All the registers which are updated with the verti-
cal sync get these values with the next vertical sync.
During this initialization procedure (approx. 60 µs) it is
not possible to access the DDP via the serial interface
(I²C). Access to other ICs via the serial bus is possible
during that time. The same initialization procedure is
started when the internal clock supervision detects that
there is no clock (in the video processing part).
Exceptions for initialization :
– CCU clock divider (5MHz), not initialized by reset
– standby clock divider (1MHz), not initialized by reset,
but clock selector switched to standby clock
During standby, only the horizontal drive pulse and the
5 MHz clock output for the control microprocessor are
active. The standby circuitry is reset when the standby
supply voltage is applied.
2.4.1. Standby Mode for VPC and DDP
In a system with the video processor VPC and the dis-
play processor DDP it is possible to realize a standby
mode where the whole signal processing is disabled and
only some basic functions are working. This is possible
because different supply pins for normal operation and
standby operation are available. The standby mode is
realized by switching off the supplies for analog frontend
(VSUPF), analog backend (VSUPO) and the normal dig-
ital supply (VSUPD). The standby supply (VSTDBY) still
has its nominal voltage. In the standby mode, all regis-
ters and counter values in the VPC and DDP are lost,
they have to be re-initialized after analog and digital sup-
plies are switched on again. The VPC still generates the
5 MHz clock which is used in the DDP as timing
reference during standby.
VSTBY
VSUP
Reset
CLK5
CLK20
VPC
DDP
Fig. 2–19: VPC & DDP Supply and Clock
To disable all the analog and digital functions, it is neces-
sary to bring the analog and digital supplies below 0.5 V.
Only this guarantees that all the normal functions are
disabled and the standby current for analog and digital
supply is at its minimum.
In the standby mode the following functions are still
available :
– crystal oscillator of VPC
– 5 MHz clock output of VPC, standby clock for DDP,
can also be used as CCU clock
– horizontal output of DDP, duty cycle set to 50 %, the 5
MHz clock is used as timing reference in standby
mode (standby clock); protection modes with safety
and horizontal flyback pins (in VPC) are not available
When the main power goes down, DDP and VPC react
in different ways. An internal power supervision, in both
VPC and DDP, generates the required power down sig-
nals.
2.4.2. DDP Power on
The DDP has its own clock and voltage supervision cir-
cuit to generate a reset signal during power on. The ini-
tialization of registers is described in section 2.4.3. ‘DDP
Standby On/Off’. The HOUT signal is disabled until a
proper CLK5 signal (5 MHz clock) has been detected.
Therefore at least one positive and negative edge with
the correct distance (two 20 MHz clocks) has to be re-
ceived. After this Clock Release signal, the HOUT
generator runs with the standby clock, which is derived
from the 5 MHz clock (divide by 5). Switching to the line
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