DDP3300A Datasheet, PDF (36/53 Pages) Micronas – Single-Chip Display and Deflection Processor

DDP 3300 A
PRELIMINARY DATA SHEET
4.5. Pin Circuits
V_SUPP
P
N
GNDD
Fig. 4–5: Output pins MSY, CSY
P
N
N
Fig. 4–6: I/O pins PR0, PR1, PR2, FPDAT
Fig. 4–7: Input pins TEST, RES, CLK5
P
N
N
Fig. 4–10: I/O pins SCL, SDA
V_SUPD
P
N
GNDD
Fig. 4–11: Input pins C[7:0], L[7:0], OSD[4:0],
FSY
V_SUPO
N
BIAS
N
GNDO
Fig. 4–12: Analog output pins ROUT, GOUT,
BOUT, SVMOUT
V_STDBY
Fig. 4–8: Input pins CLK20
V_SUPO
P P BIAS
NN
GNDO
Fig. 4–9: Input pins SAFETY, VPROT, HFLB, FBLIN,
RIN, BIN, GIN, SENSE
N
GNDO
Fig. 4–13: Output pin HOUT
N
MGND
Fig. 4–14: Output pins RSW1, RSW2
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MICRONAS INTERMETALL