DDP3300A Datasheet, PDF (32/53 Pages) Micronas – Single-Chip Display and Deflection Processor

DDP 3300 A
PRELIMINARY DATA SHEET
Pin No.
PLCC PSDIP
68-pin 64-pin
60
40
61
39
62
38
63
37
64
36
65
–
66
35
67
34
68
33
Connection
(if not used)
GNDD
GNDD
GNDD
GNDD
GNDD
X
GNDD
X
LV
Pin Name
Y5
NC
Y6
Y7
NC
GNDD
NC
VSUPP
CSY
Type Short Description
IN
IN
IN
OUT
Picture Bus Luma
Not connected
Picture Bus Luma
Picture Bus Luma (LSB)
Not connected
Ground, Digital Circuitry
Not connected
Supply Voltage, Output Pin Driver
Composite Sync Output
4.3. Pin Descriptions (Pin Numbers for PLCC68)
NC = not connected
Pin 1 – Main Sync Signal Output MSY (Fig. 4–5)
This pin supplies the front end ICs with the main horizon-
tal sync information, locked to the horizontal flyback.
Also line number, field even/odd and vertical blanking in-
formation is included.
Pin 3 – Front Sync Signal Input FSY (Fig. 4–11)
This pin gets the front horizontal sync information from
the video decoder VPC 32XX. Also skew, vertical sync,
field even/odd and PAL-plus helper line indication is in-
cluded.
Pin 4 – 5 MHz Clock Input CLK5 (Fig. 4–7)
5 MHz clock required for HOUT and CSY generation
during standby mode.
Pin 5 – Horizontal Drive HOUT (Fig. 4–13)
This open drain output supplies the drive pulse for the
horizontal output stage. The gating with the flyback
pulse is selectable by software.
Pin 6 – Standby Supply Voltage VSTDBY
In standby mode this pin supplies the horizontal drive cir-
cuitry.
Pin 7 – Horizontal Flyback Input HFLB (Fig. 4–9)
Via this pin the horizontal flyback pulse is supplied to the
DDP.
Pin 8 – Vertical Protection Input VPROT (Fig. 4–9)
The vertical protection circuitry prevents the picture tube
from burn-in in the event of a malfunction of the vertical
deflection stage. During vertical blanking, a signal level
32
of 2.5V is sensed. If a negative edge cannot be detected,
the RGB output signals are blanked.
Pin 9 – Safety Input, SAFETY (Fig. 4–9)
This is a three-level input. Low level means normal func-
tion. At the medium level RGB signals are blanked and
at high level RGB signals are blanked and horizontal
drive is shut off.
Pin 10 – I²C Clock Input SCL (Fig. 4–10)
Via this pin the clock signal for the I²C-bus is supplied.
Pin 11 – I²C Data Input/Output SDA (Fig. 4–10)
Via this pin the I²C-bus data are written to or read from
the DDP.
Pin 12 – Test Input TEST (Fig. 4–7)
This pin enables factory test modes. For normal opera-
tion it must be connected to ground.
Pin 13 – Reset Input RES (Fig. 4–7)
A low level on this pin resets the DDP.
Pin 14,15 – Range Switch for Meas. ADC RSW1 RSW2
(Fig. 4–14 )
These pins are open drain pulldown outputs. During cut-
off measurement both switches are off. During white
drive measurement RSW1 is switched off and RSW2 is
switched on. During the rest of time both switches are
on.
Pin 16 – Measurement ADC Input SENSE (Fig. 4–9)
This is the input of the analog to digital converter for the
picture and tube measurement. Three ranges of mea-
surement are selectable with RSW1 and RSW2.
MICRONAS INTERMETALL