SDA9488X Datasheet, PDF (34/87 Pages) Micronas – Cost-effective Picture-In-Picture ICs

SDA 9488X
Preliminary Data Sheet
SDA 9588X
System Description
as others can be filtered out. The XDS filter reduce traffic on the I²C bus and save
calculation power of
(both fields) is sliced
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class filter is selected,
interface. When one or
all incoming data
more class filters
are chosen, only data in field 2 is sliced. Any combination of class filters is allowed. Each
’CLASS’ is divided into ’TYPES’ which can be sorted out by the XDS-secondary filter
(XDSTPE). Any combination of type filter is allowed. Some type filter require an
appropriate class filter.
4.10.2 Widescreen Signalling (WSS)
In WSS mode (SERVICE=’1’) no filtering is possible. All sliced data is passed to the
output registers. In this case XDSTPE selects the field number of the data to be sliced.
In Europe WSS carries for instance information about aspect ratio and movie mode.
4.10.3 Indication Of New Data
The sliced and possibly filtered data is available in DATAA and DATAB. The
corresponding status bits are DATAV and SLFIELD. When new data were received,
DATAV becomes ’1’ and the controller must read DATAA, DATAB and the status
information. After both data bytes were read DATAV becomes ’0’ until new data arrives.
It must be ensured that the data polling is activated once per field (16.7 or 20 ms) or
every second field (33.3 or 40 ms), depending on the slicer configuration and inset field
frequency. The field number of the data in DATAA and DATAB can be found in
SLFIELD. If one or more XDS-class filter are activated, SLFIELD contains always ’1’.
Additionally pin 10 (INT) may flag that new data is received. Default this pin is in tri-state
mode to be compatible with Micronas' SDA9388X/9389X PIP devices. It can also be
configured by IRQCON to output a single short pulse when new data is available or
behave equal to DATAV. In the last case the output remains active until the two data
registers DATAA/DATAB are read. Both modes are useful to avoid continuos polling of
the I2C bus. The micro-controller initiates I2C transfers only when required.
while (1){
i2c_read pip4_adr, status_reg_adr, status
if (status & data_valid_mask) {
i2c_read_inc pip4_adr, dataa_reg_adr, dataa, datab, status
process_data dataa, datab, status
}
}
Figure 4-18 Example in pseudo-code for reading the data
Micronas
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