SDA9488X Datasheet, PDF (11/87 Pages) Micronas – Cost-effective Picture-In-Picture ICs

SDA 9488X
SDA 9588X
Preliminary Data Sheet
System Description
The clamping pulse can be shifted in position (CLMPIST) and length (CLMPID) to adjust
to the specific application. The ADCs are driven by a 20.25 MHz free running crystal
clock which is not related to the incoming CVBS signal.
To avoid aliasing by subsampling the CVBS signal and the Y/C signals should be
bandlimited to 10MHz. In the same manner the U/V signal frequency spectrum (SDA
9588X) should not exceed 5 MHz. The digital filtering suppresses all frequencies above
the useable spectrum.
4.1.3
Automatic Gain Control
To accommodate to different CVBS input voltages an automatic gain control has been
implemented. The chip works correctly for input voltages in the range from 0.5 to 1.5V_pp.
For best signal-to-noise ratio, the maximum CVBS amplitude is recommended if
available. The AGC behavior can be chosen out of four possibilities (AGCMDE):
The sync height serves as reference for the gain control in the typical application. When
using overflow detection only, the gain is set to maximum and is reduced whenever an
overflow occurs. This procedure will be executed again when a channel change is
detected or the gain control is manually reset by AGCRES.
Automatic Gain Control Characteristic
2
1.5
1
0.5
0
0
2
4
6
8
10
12
14
16
AGCVAL
Figure 4-2 AGC characteristic
4.1.4
Signal Magnitudes
The nominal CVBS signal with 75% color has a magnitude of 1 V_pp. The upper headroom
is left to permit signals with 100% color resulting in 1.23 V_pp. The Y signal must always
contain the sync part. Its levels correspond to the CVBS levels except for the missing
color and burst. After A/D conversion the video part is clamped to its black value and is
amplified to 224 digital steps. The nominal signal levels ensure correct brightness and
saturation. The YUV signal levels conform to the ITU 601 recommendation.
Micronas
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