SDA9488X Datasheet, PDF (22/87 Pages) Micronas – Cost-effective Picture-In-Picture ICs

SDA 9488X
SDA 9588X
Preliminary Data Sheet
System Description
As the external VSP and HSP signals may come from different devices with different
delay paths, the phase between V-sync and H-sync is adjustable (VSPDEL). An
incorrect setting of VSPDEL may result in wrong or unreliable field detection of parent
channel.
Normally a noise reduction of the incoming parent vertical pulse is performed. With this
function missing vertical pulses are compensated. The circuit works for 50/60 Hz
applications as well as progressive and 100/120Hz application. (S)VGA signals are
supposed to be very stable and therefore not supported by the noise suppression. By
means of VSPNSRQ, vertical noise suppression is switched off.
A great variety of combinations of inset and parent frequencies are possible. The
following table shows some constellations:
Inset
Parent
Frequency¹⁾ Frequency¹⁾
(HSP/VSP)
50
50i
frame
mode
correct aspect
ratio
(single pip)
correct aspect vertical
ratio
noise
(multi display) suppression
selectable
50
60i
60
50i
60
60i
50
50p
50
60p
60
50p
60
60p
50
100i
50
120i
60
100i
60
120i
50
(S)VGA
2)
60
(S)VGA
2)
1) _{standard signals supposed}
2) _{valid for some parent frequencies. Please refer to Chapter 4.7.1}
Table 4-11 Available Features with varying inset and parent standards
Micronas
4-22