EDY4016AABG-JD-F Datasheet, PDF (97/356 Pages) Micron Technology – DDR4 SDRAM

4Gb: x16 DDR4 SDRAM
Maximum Power-Saving Mode
Maximum Power-Saving Mode Entry in PDA
The sequence and timing required for the maximum power-saving mode with the per-
DRAM addressability enabled is illustrated in the figure below.
Figure 38: Maximum Power-Saving Mode Entry with PDA
Ta0
Ta1
Ta2
Tb0
Tb1
Tb3
Tb4
Tb5
Tb6
Tb7
Tb8
Tb9
Tc0
Tc1
Tc2
Td0
Td1
Td2
CK_c
CK_t
MR4[A1 = 1]
MPSM Enable)
Command DES
MRS
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
t_CKMPE
CS_n
CKE
DQS_t
DQS_c
DQ
AL + CWL
t_{PDA_S}
t_MPED
t_{PDA_H}
RESET_n
Time Break
Don’t Care
CKE Transition During Maximum Power-Saving Mode
The following figure shows how to maintain maximum power-saving mode even though
the CKE input may toggle. To prevent the device from exiting the mode, CS_n should be
HIGH at the CKE LOW-to-HIGH edge, with appropriate setup (^tMPX_S) and hold
(^tMPX_H) timings.
Figure 39: Maintaining Maximum Power-Saving Mode with CKE Transition
CLK
CMD
CS_n
CKE
t_{MPX_S} t_{MPX_HH}
RESET_n
Don’t Care
Maximum Power-Saving Mode Exit
To exit the maximum power-saving mode, CS_n should be LOW at the CKE LOW-to-
HIGH transition, with appropriate setup (^tMPX_S) and hold (^tMPX_LH) timings, as
shown in the figure below. Because the clock receivers (CK_t, CK_c) are disabled during
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
97
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.