EDY4016AABG-JD-F Datasheet, PDF (324/356 Pages) Micron Technology – DDR4 SDRAM

4Gb: x16 DDR4 SDRAM
Speed Bin Tables
Table 145: DDR4-3200 Speed Bins and Operating Conditions (Continued)
DDR4-3200 Speed Bin
CL-nRCD-nRP
Parameter
Supported CL settings with read DBI
Supported CWL settings
N/A
-JB
-JD
20-20-20
22-22-22
24-24-24
Symbol Min
Max
Min
Max
Min
Max Unit
11–24, 26, 28
12–16, 18–24, 26, 28 12, 14, 16, 19, 21, nCK
23, 28
9, 10, 11, 12, 14, 16, 9, 10, 11, 12, 14, 16, 9, 10, 11, 12, 14, 16, nCK
18, 20
18, 20
18, 20
Notes:
1. Speed Bin table is only valid with DLL enabled and gear-down mode disabled.
2. When operating in 2^tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable ^tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. ^tCK(AVG) MIN.
5. The DRAM supports 13.5ns with CL9 operation.
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
324
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