EDY4016AABG-JD-F Datasheet, PDF (157/356 Pages) Micron Technology – DDR4 SDRAM

4Gb: x16 DDR4 SDRAM
CRC Write Data Feature
MRS (that is, persistent mode), the DRAM will not write bad data to the core when a
CRC error is detected.
DBI_n and CRC Both Enabled
The DRAM computes the CRC for received written data D[71:0]. Data is not inverted
back based on DBI before it is used for computing CRC. The data is inverted back based
on DBI before it is written to the DRAM core.
DM_n and CRC Both Enabled
When both DM and write CRC are enabled in the DRAM mode register, the DRAM cal-
culates CRC before sending the write data into the array. If there is a CRC error, the
DRAM blocks the WRITE operation and discards the data. The Nonconsecutive WRITE
(BL8/BC4-OTF) with 2^tCK Preamble and Write CRC in Same or Different Bank Group and
the WRITE (BL8/BC4-OTF/Fixed) with 1^tCK Preamble and Write CRC in Same or Different
BankGroup figures in the WRITE Operation section show timing differences when DM
is enabled.
DM_n and DBI_n Conflict During Writes with CRC Enabled
Both write DBI_n and DM_n can not be enabled at the same time; read DBI_n and
DM_n can be enabled at the same time.
CRC and Write Preamble Restrictions
When write CRC is enabled:
• And 1^tCK WRITE preamble mode is enabled, a ^tCCD_S or ^tCCD_L of 4 clocks is not
allowed.
• And 2^tCK WRITE preamble mode is enabled, a ^tCCD_S or ^tCCD_L of 6 clocks is not
allowed.
CRC Simultaneous Operation Restrictions
When write CRC is enabled, neither MPR writes nor per-DRAM mode is allowed.
CRC Polynomial
The CRC polynomial used by DDR4 is the ATM-8 HEC, X⁸ + X² + X¹ + 1.
A combinatorial logic block implementation of this 8-bit CRC for 72 bits of data in-
cludes 272 two-input XOR gates contained in eight 6-XOR-gate-deep trees.
The CRC polynomial and combinatorial logic used by DDR4 is the same as used on
GDDR5.
The error coverage from the DDR4 polynomial used is shown in the following table.
Table 50: CRC Error Detection Coverage
Error Type
Random single-bit errors
Random double-bit errors
Detection Capability
100%
100%
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
157
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