EDY4016AABG-JD-F Datasheet, PDF (93/356 Pages) Micron Technology – DDR4 SDRAM

4Gb: x16 DDR4 SDRAM
Gear-Down Mode
Gear-Down Mode
The DDR4 SDRAM defaults in 1/2 rate (1N) clock mode and uses a low-frequency MRS
command (the MRS command has relaxed setup and hold) followed by a sync pulse
(first CS pulse after MRS setting) to align the proper clock edge for operating the control
lines CS_n, CKE, and ODT when in 1/4 rate (2N) mode. Gear-down mode is only sup-
ported at DDR4-2666 and faster. For operation in 1/2 rate mode, neither an MRS com-
mand or a sync pulse is required. Gear-down mode may only be entered during initiali-
zation or self refresh exit and may only be exited during self refresh exit. The general se-
quence for operation in 1/4 rate during initialization is as follows:
1. The device defaults to a 1N mode internal clock at power-up/reset.
2. Assertion of reset.
3. Assertion of CKE enables the DRAM.
4. MRS is accessed with a low-frequency N × ^tCK gear-down MRS command. (N^tCK
static MRS command is qualified by 1N CS_n. )
5. The memory controller will send a 1N sync pulse with a low-frequency N × ^tCK
NOP command. ^tSYNC_GEAR is an even number of clocks. The sync pulse is on
an even edge clock boundary from the MRS command.
6. Initialization sequence, including the expiration of ^tDLLK and ^tZQinit, starts in 2N
mode after ^tCMD_GEAR from 1N sync pulse.
The device resets to 1N gear-down mode after entering self refresh. The general se-
quence for operation in gear-down after self refresh exit is as follows:
1. MRS is set to 1, via MR3[3], with a low-frequency N × ^tCK gear-down MRS com-
mand.
a. The N^tCK static MRS command is qualified by 1N CS_n, which meets ^tXS or
t_{XS_ABORT.}
b. Only a REFRESH command may be issued to the DRAM before the N^tCK
static MRS command.
2. The DRAM controller sends a 1N sync pulse with a low-frequency N × ^tCK NOP
command.
a. ^tSYNC_GEAR is an even number of clocks.
b. The sync pulse is on even edge clock boundary from the MRS command.
3. A valid command not requiring locked DLL is available in 2N mode after
t_{CMD_GEAR from the 1N sync pulse.}
a. A valid command requiring locked DLL is available in 2N mode after ^tXSDLL
or ^tDLLK from the 1N sync pulse.
4. If operation is in 1N mode after self refresh exit, N × ^tCK MRS command or sync
pulse is not required during self refresh exit. The minimum exit delay to the first
valid command is ^tXS, or ^tXS_ABORT.
The DRAM may be changed from 2N to 1N by entering self refresh mode, which will re-
set to 1N mode. Changing from 2N to by any other means can result in loss of data and
make operation of the DRAM uncertain.
When operating in 2N gear-down mode, the following MR settings apply:
• CAS latency (MR0[6:4,2]): Even number of clocks
• Write recovery and read to precharge (MR0[11:9]): Even number of clocks
• Additive latency (MR1[4:3]): CL - 2
• CAS WRITE latency (MR2 A[5:3]): Even number of clocks
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
93
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