EDY4016AABG-JD-F Datasheet, PDF (235/356 Pages) Micron Technology – DDR4 SDRAM

4Gb: x16 DDR4 SDRAM
WRITE Operation
Figure 185: Nonconsecutive WRITE (BL8/BC4-OTF) with 1^tCK Preamble and Write CRC in Same or Dif-
ferent Bank Group
T0
T1
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
CK_c
CK_t
Command WRITE
Bank Group
BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
DQ x4,
BL = 8
DQ x8/X16,
BL = 8
DQ x4,
BC = 4 (OTF)
DQ x8/X16,
BC = 4 (OTF)
DES
DES
t_{CCD_S/L = 7}
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
BGa or
BGb
Bank
Col b
t_WPRE
WL = AL + CWL = 10
WL = AL + CWL = 10
DI
n
DI DI DI DI DI DI DI
n+1 n+2 n+3 n+4 n+5 n+6 n+7
CRC
CRC
DI
n
DI DI DI DI DI DI DI
n+1 n+2 n+3 n+4 n+5 n+6 n+7
CRC
DI DI DI DI
n n+1 n+2 n+3
CRC CRC
DI DI DI DI
n n+1 n+2 n+3
CRC
DES
DES
DES
DES
DES
DES
t_WR
4 Clocks
t_WTR
t_WPST
DI
b
DI DI DI DI DI DI DI
b+1 b+2 b+3 b+4 b+5 b+6 b+7
CRC
CRC
DI
b
DI DI DI DI DI DI DI
b+1 b+2 b+3 b+4 b+5 b+6 b+7
CRC
DI DI DI DI
b b+1 b+2 b+3
CRC CRC
DI DI DI DI
b b+1 b+2 b+3
CRC
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1^tCK, ^tCDD_S/L = 6^tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T6.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T6.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable.
7. The write recovery time (^tWR) and write timing parameter (^tWTR) are referenced from
the first rising clock edge after the last write data shown at T19.
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
235
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