EDY4016AABG-JD-F Datasheet, PDF (10/356 Pages) Micron Technology – DDR4 SDRAM

4Gb: x16 DDR4 SDRAM
Features
Figure 51: CA Parity Flow Diagram ................................................................................................................ 106
Figure 52: PDA Operation Enabled, BL8 ........................................................................................................ 108
Figure 53: PDA Operation Enabled, BC4 ........................................................................................................ 108
Figure 54: MRS PDA Exit ............................................................................................................................... 109
Figure 55: V_REFDQ Voltage Range ................................................................................................................... 110
Figure 56: Example of V_REF Set Tolerance and Step Size .................................................................................. 112
Figure 57: V_REFDQ Timing Diagram for V_REF,time Parameter .............................................................................. 113
Figure 58: V_REFDQ Training Mode Entry and Exit Timing Diagram ................................................................... 114
Figure 59: V_REF Step: Single Step Size Increment Case .................................................................................... 115
Figure 60: V_REF Step: Single Step Size Decrement Case ................................................................................... 115
Figure 61: V_REF Full Step: From V_REF,min to V_REF,maxCase .................................................................................. 116
Figure 62: V_REF Full Step: From V_REF,max to V_REF,minCase .................................................................................. 116
Figure 63: V_REFDQ Equivalent Circuit ............................................................................................................. 117
Figure 64: Connectivity Test Mode Entry ....................................................................................................... 121
Figure 65: PPR WRA – Entry .......................................................................................................................... 124
Figure 66: PPR WRA – Repair and Exit ........................................................................................................... 124
Figure 67: PPR WR – Entry ............................................................................................................................ 125
Figure 68: PPR WR – Repair and Exit .............................................................................................................. 126
Figure 69: sPPR – Entry, Repair, and Exit ........................................................................................................ 127
Figure 70: ^tRRD Timing ................................................................................................................................ 130
Figure 71: ^tFAW Timing ................................................................................................................................. 130
Figure 72: REFRESH Command Timing ......................................................................................................... 132
Figure 73: Postponing REFRESH Commands (Example) ................................................................................. 132
Figure 74: Pulling In REFRESH Commands (Example) ................................................................................... 132
Figure 75: TCR Mode Example¹ ..................................................................................................................... 134
Figure 76: 4Gb with Fine Granularity Refresh Mode Example ......................................................................... 137
Figure 77: OTF REFRESH Command Timing ................................................................................................. 138
Figure 78: Self Refresh Entry/Exit Timing ...................................................................................................... 141
Figure 79: Self Refresh Entry/Exit Timing with CAL Mode ............................................................................... 142
Figure 80: Self Refresh Abort ......................................................................................................................... 143
Figure 81: Self Refresh Exit with NOP Command ............................................................................................ 144
Figure 82: Active Power-Down Entry and Exit ................................................................................................ 146
Figure 83: Power-Down Entry After Read and Read with Auto Precharge ......................................................... 147
Figure 84: Power-Down Entry After Write and Write with Auto Precharge ........................................................ 147
Figure 85: Power-Down Entry After Write ...................................................................................................... 148
Figure 86: Precharge Power-Down Entry and Exit .......................................................................................... 148
Figure 87: REFRESH Command to Power-Down Entry ................................................................................... 149
Figure 88: Active Command to Power-Down Entry ......................................................................................... 149
Figure 89: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry .................................................. 150
Figure 90: MRS Command to Power-Down Entry ........................................................................................... 150
Figure 91: Power-Down Entry/Exit Clarifications – Case 1 .............................................................................. 151
Figure 92: Active Power-Down Entry and Exit Timing with CAL ...................................................................... 152
Figure 93: REFRESH Command to Power-Down Entry with CAL ..................................................................... 153
Figure 94: ODT Power-Down Entry with ODT Buffer Disable Mode ................................................................ 154
Figure 95: ODT Power-Down Exit with ODT Buffer Disable Mode ................................................................... 155
Figure 96: CRC Write Data Operation ............................................................................................................ 156
Figure 97: CRC Error Reporting ..................................................................................................................... 165
Figure 98: CA Parity Flow Diagram ................................................................................................................ 166
Figure 99: 1^tCK vs. 2^tCK WRITE Preamble Mode ............................................................................................ 170
Figure 100: 1^tCK vs. 2^tCK WRITE Preamble Mode, ^tCCD = 4 ............................................................................ 172
Figure 101: 1^tCK vs. 2^tCK WRITE Preamble Mode, ^tCCD = 5 ............................................................................ 173
Figure 102: 1^tCK vs. 2 ^tCK WRITE Preamble Mode, ^tCCD = 6 ........................................................................... 173
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
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