EDY4016AABG-JD-F Datasheet, PDF (343/356 Pages) Micron Technology – DDR4 SDRAM

Table 148: Electrical Characteristics and AC Timing Parameters (Continued)
DDR4-2666
Reserved
DDR4-3200
Reserved
Parameter
Symbol
Min Max Min Max Min Max Min Max
CAS_n-to-CAS_n command delay to same
bank group
t_{CCD_L}
MIN = –
greater
of 4CK
or 5ns
MIN = –
greater
of 4CK
or 5ns
Auto precharge write recovery + pre-
charge time
t_{DAL (MIN)}
MIN = WR + ROUNDUP^tRP/^tCK (AVG); MAX = N/A
MRS Command Timing
MRS command cycle time
t_MRD
9
–
10
–
MRS command cycle time in PDA mode
t_{MRD_PDA}
MIN = greater of (16nCK, 10ns)
MRS command cycle time in CAL mode
t_{MRD_CAL}
MIN = ^tMOD + ^tCAL
MRS command update delay in PDA
mode
t_MOD
MIN = greater of (24nCK, 15ns)
MRS command update delay
t_{MOD_PDA}
MIN = ^tMOD
MRS command update delay in CAL
mode
t_{MOD_CAL}
MIN = ^tMOD + ^tCAL
MRS commandto DQS drive in preamble
training
t_SDO
MIN = ^tMOD + 9ns
MPR Command Timing
Multipurpose register recovery time
t_MPRR
MIN = 1nCK
Multipurpose register write recovery time ^tWR_MPRR
MIN = ^tMOD + AL + PL
CRC Error Reporting Timing
CRC error to ALERT_n latency
t_{CRC_ALERT}
3
13
3
13
CRC ALERT_n pulse width
t_{CRC_ALERT_P 6}
10
W
6
10
CA Parity Timing
Parity latency
PL
5
–
6
–
Commands uncertain to be executed dur-
ing this time
t_{PAR_UN-}
KNOWN
–
PL
–
PL
Delay from errant command to ALERT_n ^tPAR_ALERT_O –
PL +
assertion
N
6ns
–
PL +
6ns
Pulse width of ALERT_n signal when as- ^tPAR_ALERT_P 80
160
serted
W
96
192
Unit
CK
CK
CK
CK
CK
CK
CK
CK
ns
CK
CK
CK
CK
CK
Notes
14
1
1