MT47H64M8B6-25ELDTR Datasheet, PDF (94/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
READ
Figure 45: Consecutive READ Bursts
CK#
CK
Command
Address
T0
READ
Bank,
Col n
DQS, DQS#
DQ
T1
NOP
tCCD
RL = 3
T2
READ
Bank,
Col b
T3 T3n T4 T4n T5 T5n T6 T6n
NOP
NOP
NOP
NOP
DO
DO
n
b
CK#
CK
Command
Address
T0
READ
Bank,
Col n
DQS, DQS#
DQ
T1
T2 T2n T3 T3n T4 T4n T5 T5n T6 T6n
NOP
tCCD
RL = 4
READ
Bank,
Col b
NOP
NOP
NOP
NOP
DO
DO
n
b
Transitioning Data
Don’t Care
Notes:
1. DO n (or b) = data-out from column n (or column b).
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following
DO n.
4. Three subsequent elements of data-out appear in the programmed order following
DO b.
5. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.
6. Example applies only when READ commands are issued to same device.
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
94
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