MT47H64M8B6-25ELDTR Datasheet, PDF (62/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Table 31: DDR2-400/533 ^tDS, ^tDH Derating Values with Differential Strobe
All units are shown in picoseconds
DQ
Slew
Rate
(V/ns)
4.0 V/ns
ΔΔ
t_DS t_DH
3.0 V/ns
ΔΔ
t_DS t_DH
2.0 V/ns
ΔΔ
t_DS t_DH
DQS, DQS# Differential Slew Rate
1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns
ΔΔΔΔΔΔΔΔ
t_DS t_DH t_DS t_DH t_DS t_DH t_DS t_DH
1.0 V/ns
ΔΔ
t_DS t_DH
0.8 V/ns
ΔΔ
t_DS t_DH
2.0 125 45 125 45 125 45 – – – – – – – – – – – –
1.5 83 21 83 21 83 21 95 33 – – – – – – – – – –
1.0 0 0 0 0 0 0 12 12 24 24 – – – – – – – –
0.9 – – –11 –14 –11 –14 1 –2 13 10 25 22 – – – – – –
0.8 – – – – –25 –31 –13 –19 –1 –7 11 5 23 17 – – – –
0.7 – – – – – – –31 –42 –19 –30 –7 –18 5 –6 17 6 – –
0.6 – – – – – – – – –43 –59 –31 –47 –19 –35 –7 –23 5 –11
0.5 – – – – – – – – – – –74 –89 –62 –77 –50 –65 –38 –53
0.4 – – – – – – – – – – – – –127 –140 –115 –128 –103 –116
Notes:
1. For all input signals, the total ^tDS and ^tDH required is calculated by adding the data
sheet value to the derating value listed in Table 31.
2. ^tDS nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of V_REF(DC) and the first crossing of V_IH(AC)min. ^tDS nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of V_REF(DC) and the first cross-
ing of V_IL(AC)max. If the actual signal is always earlier than the nominal slew rate line be-
tween the shaded “V_REF(DC) to AC region,” use the nominal slew rate for the derating
value (see Figure 26 (page 66)). If the actual signal is later than the nominal slew rate
line anywhere between the shaded “V_REF(DC) to AC region,” the slew rate of a tangent
line to the actual signal from the AC level to DC level is used for the derating value (see
Figure 27 (page 66)).
3. ^tDH nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of V_IL(DC)max and the first crossing of V_REF(DC). ^tDH nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of V_IH(DC)min and the first
crossing of V_REF(DC). If the actual signal is always later than the nominal slew rate line
between the shaded “DC level to V_REF(DC) region,” use the nominal slew rate for the de-
rating value (see Figure 28 (page 67)). If the actual signal is earlier than the nominal
slew rate line anywhere between shaded “DC to V_REF(DC) region,” the slew rate of a tan-
gent line to the actual signal from the DC level to V_REF(DC) level is used for the derating
value (see Figure 29 (page 67)).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached V_IH[AC]/V_IL[AC] at the time of the rising clock transition), a valid in-
put signal is still required to complete the transition and reach V_IH(AC)/V_IL(AC).
5. For slew rates between the values listed in this table, the derating values may be ob-
tained by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 33 (page 64) are the
DQS single-ended slew rate derating with DQS referenced at V_REF and DQ referenced at
the logic levels ^tDS_b and ^tDH_b. Converting the derated base values from DQ referenced
to the AC/DC trip points to DQ referenced to V_REF is listed in Table 35 (page 65) and
Table 36 (page 65). Table 35 provides the V_REF-based fully derated values for the DQ
(^tDS_a and ^tDH_a) for DDR2-533. Table 36 provides the V_REF-based fully derated values for
the DQ (^tDS_a and ^tDH_a) for DDR2-400.
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
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