MT47H64M8B6-25ELDTR Datasheet, PDF (109/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
WRITE
Figure 61: WRITE-to-PRECHARGE
CK#
CK
Command
T0
WRITE
Address
Bank a,
Col b
tDQSS _(NOM)
DQS#
DQS
DQ
DM
tDQSS _(MIN)
DQS#
DQS
DQ
DM
tDQSS _(MAX)
DQS#
DQS
DQ
DM
T1
T2
T2n
T3 T3n
T4
NOP
NOP
NOP
NOP
WL + ^tDQSS
1
DI
b
WL - ^tDQSS
1
DI
b
WL + ^tDQSS
1
DI
b
T5
T6
NOP
NOP
tWR
T7
PRE
tRP
Bank,
(a or all)
Transitioning Data
Don’t Care
Notes:
1. Subsequent rising DQS signals must align to the clock within ^tDQSS.
2. DI b = data-in for column b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI b.
4. BL = 4, CL = 3, AL = 0; thus, WL = 2.
5. ^tWR is referenced from the first positive CK edge after the last data-in pair.
6. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE
and WRITE commands may be to different banks, in which case ^tWR is not required and
the PRECHARGE command could be applied earlier.
7. A10 is LOW with the WRITE command (auto precharge is disabled).
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
109
Micron Technology, Inc. reserves the right to change products or specifications without notice.
‹ 2004 Micron Technology, Inc. All rights reserved.