MT47H64M8B6-25ELDTR Datasheet, PDF (126/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
Reset
Figure 78: RESET Function
T0
CK#
CK
CKE
ODT
Command
READ
DM3
T1
NOP2
T2
READ
T3
NOP2
T4
T5
tDELAY
1
NOP2
tCK ^Ta0
Tb0
tCL tCL tCKE _(MIN)
NOP2
PRE
Address
Col n
A10
Col n
All banks
Bank address
DQS3
DQ3
R_TT
Bank a
High-Z
High-Z
Bank b
DO DO DO
High-Z

High-Z
High-Z
System
RESET
Indicates a break in
time scale
Unknown
R_TT On
T = 400ns (MIN)
tRPA
Start of normal5
initialization
sequence
Transitioning Data
Don’t Care
Notes:
1. V_DD, V_DDL, V_DDQ, V_TT, and V_REF must be valid at all times.
2. Either NOP or DESELECT command may be applied.
3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS
represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropri-
ate configuration (x4, x8, x16).
4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the
completion of the burst.
5. Initialization timing is shown in Figure 41 (page 87).
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
126
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