MT47H64M8B6-25ELDTR Datasheet, PDF (83/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)
On-Die Termination (ODT)
ODT effective resistance, R_TT(EFF), is defined by bits E2 and E6 of the EMR, as shown in
Figure 36 (page 81). The ODT feature is designed to improve signal integrity of the
memory channel by allowing the DDR2 SDRAM controller to independently turn on/off
ODT for any or all devices. R_TT effective resistance values of 50ΩΩ, and 150Ω are se-
lectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/
LDQS#, DM, and UDM/LDM signal. Bits (E6, E2) determine what ODT resistance is en-
abled by turning on/off sw1, sw2, or sw3. The ODT effective resistance value is selected
by enabling switch sw1, which enables all R1 values that are 150Ω each, enabling an ef-
fective resistance of 75Ω (R_{TT2 [EFF]} = R2/2). Similarly, if sw2 is enabled, all R2 values that
are 300Ω each, enable an effective ODT resistance of 150Ω (R_TT2[EFF] = R2/2). Switch sw3
enables R1 values of 100Ω, enabling effective resistance of 50Ω. Reserved states should
not be used, as an unknown operation or incompatibility with future versions may re-
sult.
The ODT control ball is used to determine when R_TT(EFF) is turned on and off, assuming
ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and ODT input
ball are only used during active, active power-down (both fast-exit and slow-exit
modes), and precharge power-down modes of operation.
ODT must be turned off prior to entering self refresh mode. During power-up and initi-
alization of the DDR2 SDRAM, ODT should be disabled until the EMR command is is-
sued. This will enable the ODT feature, at which point the ODT ball will determine the
R_TT(EFF) value. Anytime the EMR enables the ODT function, ODT may not be driven
HIGH until eight clocks after the EMR has been enabled (see Figure 79 (page 128) for
ODT timing diagrams).
Off-Chip Driver (OCD) Impedance Calibration
The OFF-CHIP DRIVER function is an optional DDR2 JEDEC feature not supported by
Micron and thereby must be set to the default state. Enabling OCD beyond the default
settings will alter the I/O drive characteristics and the timing and output I/O specifica-
tions will no longer be valid (see Initialization section for proper setting of OCD de-
faults).
Posted CAS Additive Latency (AL)
Posted CAS additive latency (AL) is supported to make the command and data bus effi-
cient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as
shown in Figure 36. Bits E3–E5 allow the user to program the DDR2 SDRAM with an AL
of 0, 1, 2, 3, 4, 5, or 6 clocks. Reserved states should not be used as an unknown opera-
tion or incompatibility with future versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued
prior to ^tRCD (MIN) with the requirement that AL ≤ ^tRCD (MIN). A typical application
using this feature would set AL = ^tRCD (MIN) - 1 × ^tCK. The READ or WRITE command
is held for the time of the AL before it is issued internally to the DDR2 SDRAM device.
RL is controlled by the sum of AL and CL; RL = AL + CL. WRITE latency (WL) is equal to
RL minus one clock; WL = AL + CL - 1 × ^tCK. An example of RL is shown in Figure 37
(page 84). An example of a WL is shown in Figure 38 (page 84).
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
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