MT47H64M8B6-25ELDTR Datasheet, PDF (107/133 Pages) Micron Technology – 512Mb: x4, x8, x16 DDR2 SDRAM

512Mb: x4, x8, x16 DDR2 SDRAM
WRITE
Figure 59: WRITE Interrupted by WRITE
CK#
CK
Command
T0
WRITE1 a
Address Valid5
A10
DQS, DQS#
T1
NOP2
T2
WRITE3 b
Valid5
Valid6
T3
NOP2
T4
NOP2
7
T5
NOP2
7
T6
NOP2
T7
Valid4
T8
Valid4
T9
Valid4
7
7
7
DQ
WL = 3
2-clock requirement
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
a a+1 a+2 a+3
b
b+1 b+2 b+3 b+4 b+5 b+6 b+7
WL = 3
Transitioning Data
Don’t Care
Notes:
1. BL = 8 required and auto precharge must be disabled (A10 = LOW).
2. The NOP or COMMAND INHIBIT commands are valid. The PRECHARGE command cannot
be issued to banks used for WRITEs at T0 and T2.
3. The interrupting WRITE command must be issued exactly 2 × ^tCK from previous WRITE.
4. The earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 + ^tWR where ^tWR
starts with T7 and not T5 (because BL = 8 from MR and not the truncated length).
5. The WRITE command can be issued to any valid bank and row address (WRITE command
at T0 and T2 can be either same bank or different bank).
6. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the in-
terrupting WRITE command.
7. Subsequent rising DQS signals must align to the clock within ^tDQSS.
8. Example shown uses AL = 0; CL = 4, BL = 8.
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. T 2/12 EN
107
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