MT41K512M4 Datasheet, PDF (93/207 Pages) Micron Technology – 8n-bit prefetch architecture

2Gb: x4, x8, x16 DDR3L SDRAM
Command and Address Setup, Hold, and Derating
Table 58: DDR3L Command and Address Setup and Hold Values 1 V/ns Referenced – AC/DC-Based
Symbol
t_{IS(base, AC160)}
t_{IS(base, AC135)}
t_{IS(base, AC125)}
t_{IH(base, DC90)}
800
1066
1333
1600
1866
Unit
215
140
80
60
–
ps
365
290
205
185
65
ps
–
–
–
–
150
ps
285
210
150
130
110
ps
Reference
V_IH(AC)/V_IL(AC)
V_IH(AC)/V_IL(AC)
V_IH(AC)/V_IL(AC)
V_IH(DC)/V_IL(DC)
Table 59: DDR3L-800/1066/1333/1600 Derating Values ^tIS/^tIH – AC160/DC90-Based
Δ^tIS, Δ^tIH Derating (ps) – AC/DC-Based
CMD/ADDR
Slew Rate ^{4.0 V/ns}
V/ns
Δ^tIS Δ^tIH
3.0 V/ns
Δ^tIS Δ^tIH
CK, CK# Differential Slew Rate
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns
Δ^tIS Δ^tIH Δ^tIS Δ^tIH Δ^tIS Δ^tIH Δ^tIS Δ^tIH
1.2 V/ns
Δ^tIS Δ^tIH
1.0 V/ns
Δ^tIS Δ^tIH
2.0
80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 95
1.5
53 30 53 30 53 30 61 38 69 46 77 54 85 64 93 80
1.0
0
0
0
0
0
0
8
8 16 16 24 24 32 34 40 50
0.9
–1 –3 –1 –3 –1 –3 7
5 15 13 23 21 31 31 39 47
0.8
–3 –8 –3 –8 –3 –8 5
1 13 9 21 17 29 27 37 43
0.7
–5 –13 –5 –13 –5 –13 3 –5 11 3 19 11 27 21 35 37
0.6
–8 –20 –8 –20 –8 –20 0 –12 8 –4 16 4 24 14 32 30
0.5
–20 –30 –20 –30 –20 –30 –12 –22 –4 –14 4 –6 12 4 20 20
0.4
–40 –45 –40 –45 –40 –45 –32 –37 –24 –29 –16 –21 –8 –11 0
5
Table 60: DDR3L-800/1066/1333/1600 Derating Values for ^tIS/^tIH – AC135/DC90-Based
Δ^tIS, Δ^tIH Derating (ps) – AC/DC-Based
CMD/ADDR
Slew Rate ^{4.0 V/ns}
V/ns
Δ^tIS Δ^tIH
3.0 V/ns
Δ^tIS Δ^tIH
CK, CK# Differential Slew Rate
2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns
Δ^tIS Δ^tIH Δ^tIS Δ^tIH Δ^tIS Δ^tIH Δ^tIS Δ^tIH
1.2 V/ns
Δ^tIS Δ^tIH
1.0 V/ns
Δ^tIS Δ^tIH
2.0
68 45 68 45 68 45 76 53 84 61 92 69 100 79 108 95
1.5
45 30 45 30 45 30 53 38 61 46 69 54 77 64 85 80
1.0
0
0
0
0
0
0
8
8 16 16 24 24 32 34 40 50
0.9
2 –3 2 –3 2 –3 10 5 18 13 26 21 34 31 42 47
0.8
3 –8 3 –8 3 –8 11 1 19 9 27 17 35 27 43 43
0.7
6 –13 6 –13 6 –13 14 –5 22 3 30 11 38 21 46 37
0.6
9 –20 9 –20 9 –20 17 –12 25 –4 33 4 41 14 49 30
0.5
5 –30 5 –30 5 –30 13 –22 21 –14 29 –6 37 4 45 20
0.4
–3 –45 –3 –45 –3 –45 6 –37 14 –29 22 –21 30 –11 38 5
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2Gb_DDR3L.pdf - Rev. L 10/14 EN
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