MT41K512M4 Datasheet, PDF (159/207 Pages) Micron Technology – 8n-bit prefetch architecture

Figure 75: Data Output Timing – ^tDQSQ and Data Valid Window
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK#
CK
Command¹
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
RL = AL + CL
Address²
Bank,
Col n
DQS, DQS#
DQ³ (last data valid)
DQ³ (first data no longer valid)
All DQ collectively
t_{DQSQ (MAX)}
t_{LZDQ (MIN)}
t_{DQSQ (MAX)}
t_RPST
t_{HZDQ (MAX)}
t_RPRE
t_QH
t_QH
DO
n
DO
DO
DO
DO
DO
DO
DO
n+1 n+2 n+3 n+4 n+5 n+6 n+7
DO
DO
DO
DO
DO
DO
DO
DO
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
DO
DO
DO
DO
DO
DO
DO
DO
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Data valid
Data valid
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at
T0.
3. DO n = data-out from column n.
4. BL8, RL = 5 (AL = 0, CL = 5).
5. Output timings are referenced to V_DDQ/2 and DLL on and locked.
6. ^tDQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to CK.
7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can be early or late within
a burst.