MT41K512M4 Datasheet, PDF (85/207 Pages) Micron Technology – 8n-bit prefetch architecture

2Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
Table 57: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter
Data hold time from DQS, Base (specification) @
DQS#
2 V/ns
V_REF @ 2 V/ns
Minimum data pulse width
DQ Output Timing
DQS, DQS# to DQ skew, per access
DQ output hold time from DQS, DQS#
DQ Low-Z time from CK, CK#
DQ High-Z time from CK, CK#
DQ Strobe Input Timing
DQS, DQS# rising to CK, CK# rising
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse width
DQS, DQS# falling setup to CK, CK# rising
DQS, DQS# falling hold from CK, CK# rising
DQS, DQS# differential WRITE preamble
DQS, DQS# differential WRITE postamble
DQ Strobe Output Timing
DQS, DQS# rising to/from rising CK, CK#
DQS, DQS# rising to/from rising CK, CK# when
DLL is disabled
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# Low-Z time (RL - 1)
DQS, DQS# High-Z time (RL + BL/2)
DQS, DQS# differential READ preamble
DQS, DQS# differential READ postamble
Command and Address Timing
DLL locking time
CTRL, CMD, ADDR
Base (specification)
setup to CK,CK#
V_REF @ 1 V/ns
CTRL, CMD, ADDR
Base (specification)
setup to CK,CK#
V_REF @ 1 V/ns
CTRL, CMD, ADDR hold Base (specification)
from CK,CK#
V_REF @ 1 V/ns
Minimum CTRL, CMD, ADDR pulse width
Symbol
t_DH
(DC90)
t_DIPW
t_DQSQ
t_QH
t_LZDQ
t_HZDQ
t_DQSS
t_DQSL
t_DQSH
t_DSS
t_DSH
t_WPRE
t_WPST
t_DQSCK
t_DQSCK
(DLL_DIS)
t_QSH
t_QSL
t_LZDQS
t_HZDQS
t_RPRE
t_RPST
t_DLLK
t_IS
(AC135)
t_IS
(AC125)
t_IH
(DC90)
t_IPW
DDR3L-1866
Min
Max
75
–
110
–
320
–
Unit
ps
ps
ps
Notes
18, 19
19, 20
41
–
0.38
–390
–
85
ps
–
t_{CK (AVG)}
21
195
ps
22, 23
195
ps
22, 23
–0.27
0.27
CK
25
0.45
0.55
CK
0.45
0.55
CK
0.18
–
CK
25
0.18
–
CK
25
0.9
–
CK
0.3
–
CK
–195
195
ps
1
10
ns
0.40
–
CK
0.40
–
CK
–390
195
ps
–
195
ps
0.9
Note 24
CK
0.3
Note 27
CK
23
26
21
21
22, 23
22, 23
23, 24
23, 27
512
–
65
–
200
–
150
–
275
–
110
–
200
–
535
–
CK
28
ps
29, 30, 44
ps
20, 30
ps
29, 30, 44
ps
20, 30
ps
29, 30
ps
20, 30
ps
41
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. L 10/14 EN
85
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