MT41K512M4 Datasheet, PDF (90/207 Pages) Micron Technology – 8n-bit prefetch architecture

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2Gb_DDR3L.pdf - Rev. L 10/14 EN
2Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
14. ^tCH (ABS) is the absolute instantaneous clock high pulse width as measured from one
rising edge to the following falling edge.
15. ^tCL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall-
ing edge to the following rising edge.
16. The cycle-to-cycle jitter ^tJITcc is the amount the clock period can deviate from one cycle
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
17. The cumulative jitter error ^tERRnper, where n is the number of clocks between 2 and 50,
is the amount of clock time allowed to accumulate consecutively away from the average
clock over n number of clock cycles.
18. ^tDS (base) and ^tDH (base) values are for a single-ended 1 V/ns slew rate DQs (DQs are at
2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns slew rate differential DQS, DQS#; when
DQ single-ended slew rate is 2V/ns, the DQS differential slew rate is 4V/ns.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-
tion edge to its respective data strobe signal (DQS, DQS#) crossing.
20. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to V_REF when the slew rate is 1 V/ns (DQs are at 2V/ns for
DDR3-1866 and DDR3-2133). These values, with a slew rate of 1 V/ns (DQs are at 2V/ns
for DDR3-1866 and DDR3-2133), are for reference only.
21. When the device is operated with input clock jitter, this parameter needs to be derated
by the actual ^tJITper (larger of ^tJITper (MIN) or ^tJITper (MAX) of the input clock (output
deratings are relative to the SDRAM input clock).
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output pa-
rameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The fol-
lowing parameters are required to be derated by subtracting ^tERR10per (MAX): ^tDQSCK
(MIN), ^tLZDQS (MIN), ^tLZDQ (MIN), and ^tAON (MIN). The following parameters are re-
quired to be derated by subtracting ^tERR10per (MIN): ^tDQSCK (MAX), ^tHZ (MAX), ^tLZDQS
(MAX), ^tLZDQ (MAX), and ^tAON (MAX). The parameter ^tRPRE (MIN) is derated by sub-
tracting ^tJITper (MAX), while ^tRPRE (MAX) is derated by subtracting ^tJITper (MIN).
24. The maximum preamble is bound by ^tLZDQS (MAX).
25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re-
spective clock signal (CK, CK#) crossing. The specification values are not affected by the
amount of clock jitter applied, as these are relative to the clock signal crossing. These
parameters should be met whether clock jitter is present.
26. The ^tDQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.
27. The maximum postamble is bound by ^tHZDQS (MAX).
28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT com-
mands. In addition, after any change of latency ^tXPDLL, timing must be met.
29. ^tIS (base) and ^tIH (base) values are for a single-ended 1 V/ns control/command/address
slew rate and 2 V/ns CK, CK# differential slew rate.
30. These parameters are measured from a command/address signal transition edge to its
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.
31. For these parameters, the DDR3 SDRAM device supports ^tnPARAM (nCK) = RU(^tPARAM
[ns]/^tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-
ple, the device will support ^tnRP (nCK) = RU(^tRP/^tCK[AVG]) if all input clock jitter specifi-
cations are met. This means that for DDR3-800 6-6-6, of which ^tRP = 5ns, the device will
support ^tnRP = RU(^tRP/^tCK[AVG]) = 6 as long as the input clock jitter specifications are
met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.
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