MT41K512M4 Datasheet, PDF (192/207 Pages) Micron Technology – 8n-bit prefetch architecture

Figure 109: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
CK#
CK
Command
T0
NOP
Address
T1
WRS8
Valid
T2
T3
NOP
NOP
ODTLcnw
ODTLon
T4
NOP
ODTH8
T5
NOP
T6
NOP
T7
NOP
T8
NOP
T9
NOP
ODTLoff
T10
NOP
T11
NOP
ODT
R_TT
t_{ADC (MAX)}
t_{AON (MIN)}
ODTLcwn8
R_TT(WR)
t_{AOF (MIN)}
t_{AOF (MAX)}
DQS, DQS#
WL
DQ
DI
DI
DI
DI
DI
DI
DI
DI
b
b+1 b+2 b+3 b+4 b+5 b+6 b+7
Transitioning
Don’t Care
Notes: 1. Via MRS or OTF; AL = 0, CWL = 5. If R_TT,nom can be either enabled or disabled, ODT can be HIGH. R_TT(WR) is enabled.
2. In this example, ODTH8 = 6 is satisfied exactly.