MT41K512M4 Datasheet, PDF (57/207 Pages) Micron Technology – 8n-bit prefetch architecture

Figure 23: ^tADC Definition
2Gb: x4, x8, x16 DDR3L SDRAM
ODT Characteristics
Begin point: Rising edge of CK - CK#
defined by the end point of ODTLcnw
CK
Begin point: Rising edge of CK - CK# defined by
the end point of ODTLcwn4 or ODTLcwn8
CK#
tADC
tADC
V_DDQ/2
DQ, DM
DQS, DQS#
TDQS, TDQS#
V_RTT,nom
End point:
Extrapolated
point at V_RTT,nom
T_SW21
T_SW11
V_SW1
V_SW2
V_RTT(WR)
T_SW22
V_RTT,nom
T_SW12
End point: Extrapolated point at V_RTT(WR)
V_SSQ
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. L 10/14 EN
57
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