MT41K512M4 Datasheet, PDF (1/207 Pages) Micron Technology – 8n-bit prefetch architecture

2Gb: x4, x8, x16 DDR3L SDRAM
Description
DDR3L SDRAM
MT41K512M4 – 64 Meg x 4 x 8 banks
MT41K256M8 – 32 Meg x 8 x 8 banks
MT41K128M16 – 16 Meg x 16 x 8 banks
Description
The 1.35V DDR3L SDRAM device is a low-voltage ver-
sion of the 1.5V DDR3 SDRAM device. Refer to the
DDR3 (1.5V) SDRAM data sheet specifications when
running in 1.5V compatible mode.
Features
• V_DD = V_DDQ = 1.35V (1.283–1.45V)
• Backward-compatible to V_DD = V_DDQ = 1.5V ±0.075V
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• T_C of 0°C to +95°C
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Options
• Configuration
– 512 Meg x 4
– 256 Meg x 8
– 128 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 10.5mm)
Rev. K
• FBGA package (Pb-free) – x16
– 96-ball FBGA (8mm x 14mm)
Rev. K
• Timing – cycle time
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.875ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C ≤ T_C ≤ +95°C)
– Industrial (–40°C ≤ T_C ≤ +95°C)
• Revision
Marking
512M4
256M8
128M16
DA
JT
-107
-125
-15E
-187E
None
IT
:K
Table 1: Key Timing Parameters
Speed Grade
-107^{1, 2, 3}
-125^{1, 2}
-15E¹
-187E
Data Rate (MT/s)
1866
1600
1333
1066
Target ^tRCD-^tRP-CL
13-13-13
11-11-11
9-9-9
7-7-7
Notes: 1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-107).
t_{RCD (ns)}
13.91
13.75
13.5
13.1
t_{RP (ns)}
13.91
13.75
13.5
13.1
CL (ns)
13.91
13.75
13.5
13.1
PDF: 09005aef83ed2952
2Gb_DDR3L.pdf - Rev. L 10/14 EN
1
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Products and specifications discussed herein are subject to change by Micron without notice.