MT49H32M9 Datasheet, PDF (72/76 Pages) Micron Technology – 288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II

288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
IEEE 1149.1 Serial Boundary Scan (JTAG)
correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/
PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the
shift-DR state. This places the boundary scan register between the TDI and TDO balls.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed
in a shift-DR state, the bypass register is placed between TDI and TDO. The advantage of
the BYPASS instruction is that it shortens the boundary scan path when multiple devices
are connected together on a board.
Reserved for Future Use
The remaining instructions are not implemented but are reserved for future use. Do not
use these instructions.
Figure 45: JTAG Operation – Loading Instruction Code and Shifting Out Data
T0
TCK
TMS
TDI
TAP
CONTROLLER
STATE
Test-Logic-
Reset
TDO
T1
Run-Test
Idle
T2
Select-DR-
SCAN
T3
T4
Select-IR-
SCAN
Capture-IR
T5
Shift-IR
T6
((
))
((
))
((
))
((
))
((
))
((
))
((
Shift-IR
))
((
))
((
))
((
))
8-bit instruction code
T7
Exit 1-IR
T8
Pause-IR
T9
Pause-IR
T10
TCK
TMS
TDI
TAP
CONTROLLER
STATE
Exit 2-IR
TDO
T11
Update-IR
T12
T13
Select-DR-
Scan
Capture-DR
T14
Shift-DR
T15
((
))
((
))
((
))
((
))
((
))
((
))
((
Shift-DR
))
((
))
T16
Exit1-DR
T17
Update-DR
((
))
((
))
n-bit register between TDI and TDO
T18
Run-Test
Idle
TRANSITIONING DATA
T19
Run-Test
Idle
DON’T CARE
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
71
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