MT49H32M9 Datasheet, PDF (70/76 Pages) Micron Technology – 288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II

288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
IEEE 1149.1 Serial Boundary Scan (JTAG)
Performing a TAP RESET
A reset is performed by forcing TMS HIGH (VDDQ) for five rising edges of TCK. This
RESET does not affect the operation of the RLDRAM and may be performed while the
RLDRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and allow data to be scanned
into and out of the RLDRAM test circuitry. Only one register can be selected at a time
through the instruction register. Data is serially loaded into the TDI ball on the rising
edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is
loaded during the update-IR state of the TAP controller. Upon power-up, the instruction
register is loaded with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the capture-IR state, the two LSBs are loaded with a binary
“01” pattern to allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous
to skip certain chips. The bypass register is a single-bit register that can be placed
between the TDI and TDO balls. This allows data to be shifted through the RLDRAM
with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is
executed.
Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the
RLDRAM. Several balls are also included in the scan register to reserved balls. The
RLDRAM has a 113-bit register.
The boundary scan register is loaded with the contents of the RAM I/O ring when the
TAP controller is in the capture-DR state and is then placed between the TDI and TDO
balls when the controller is moved to the shift-DR state.
Table 29 on page 74 shows the order in which the bits are connected. Each bit corre-
sponds to one of the balls on the RLDRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state
when the IDCODE command is loaded in the instruction register. The IDCODE is hard-
wired into the RLDRAM and can be shifted out when the TAP controller is in the shift-DR
state. The ID register has a vendor code and other information described in Table 26 on
page 73.
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_II_CIO.Core.fm - Rev A 9/07 EN
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