EDY4016AABG-DR-F Datasheet, PDF (35/356 Pages) Micron Technology – Databus write cyclic redundancy check (CRC)

4Gb: x16 DDR4 SDRAM
Mode Register 0
Table 6: MR0 Register Definition (Continued)
Mode
Register
8
7
12, 6:4, 2
3
1:0
Description
DLL reset
0 = No
1 = Yes
Test mode (TM) – Manufacturer use only
0 = Normal operating mode, must be programmed to 0
CAS latency (CL) – Delay in clock cycles from the internal READ command to first data-out
00000 = 9 clocks¹
00001 = 10 clocks
00010 = 11 clocks¹
00011 = 12 clocks
00100 = 13 clocks¹
00101 = 14 clocks
00110 = 15 clocks¹
00111 = 16 clocks
01000 = 18 clocks
01001 = 20 clocks
01010 = 22 clocks
01011 = 24 clocks
01100 = 23 clocks¹
01101 = 17 clocks¹
01110 = 19 clocks¹
01111 = 21 clocks ¹
10000 = 25 clocks (3DS use only)
10001 = 26 clocks
10010 = 27 clocks (3DS use only)
10011 = 28 clocks
10100 = 29 clocks¹
10101 = 30 clocks
10110 = 31 clocks¹
10111 = 32 clocks
Burst type (BT) – Data burst ordering within a READ or WRITE burst access
0 = Nibble sequential
1 = Interleave
Burst length (BL) – Data burst size associated with each read or write access
00 = BL8 (fixed)
01 = BC4 or BL8 (on-the-fly)
10 = BC4 (fixed)
11 = Reserved
Note: 1. Not allowed when 1/4 rate gear-down mode is enabled.
Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order.
The ordering of accesses within a burst is determined by the burst length, burst type,
and the starting column address as shown in the following table. Burst length options
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
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