EDY4016AABG-DR-F Datasheet, PDF (322/356 Pages) Micron Technology – Databus write cyclic redundancy check (CRC)

4Gb: x16 DDR4 SDRAM
Speed Bin Tables
2. When operating in 2^tCK WRITE preamble mode, CWL must be programmed to a value
at least 1 clock greater than the lowest CWL setting supported in the applicable ^tCK
range.
3. The programmed value of CWL must be less than or equal to programmed value of CL.
4. 13.32ns is the minimum value of ^tAA and ^tRP when operating at DDR4-2400 at ^tCK(AVG)
MIN = 0.833ns and is only a reference that does not consider the down binning strategy
that 13.33ns supports.
5. ^tCK(AVG) MIN.
6. The DRAM supports 13.92ns with CL13 operation, 14.07ns with CL15 operation, and
14.16ns with CL17 operation at defined clock rates.
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
322
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