EDY4016AABG-DR-F Datasheet, PDF (231/356 Pages) Micron Technology – Databus write cyclic redundancy check (CRC)

4Gb: x16 DDR4 SDRAM
WRITE Operation
Figure 181: WRITE (BC4-Fixed) with 1^tCK Preamble and DBI
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK_c
CK_t
Command WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
WL = AL + CWL = 9
2 Clocks
t_WR
t_WTR
Address BGa
Address
Bank,
Col n
BC4 (Fixed) Opertaion
DQS_t,
DQS_c
DQ
DI DI DI DI
n n+1 n+2 n+3
DBI_n
DI DI DI DI
n n+1 n+2 n+3
Transitioning Data
Don’t Care
Notes:
1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1^tCK.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disa-
bled.
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
231
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