EDY4016AABG-DR-F Datasheet, PDF (171/356 Pages) Micron Technology – Databus write cyclic redundancy check (CRC)

4Gb: x16 DDR4 SDRAM
Programmable Preamble Modes and DQS Postambles
CWL has special considerations when in the 2^tCK WRITE preamble mode. The CWL val-
ue selected in MR2[5:3], as seen in table below, requires at least one additional clock
when the primary CWL value and 2^tCK WRITE preamble mode are used; no additional
clocks are required when the alternate CWL value and 2^tCK WRITE preamble mode are
used.
Table 65: CWL Selection
Speed Bin
DDR4-1600
DDR4-1866
DDR4-2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
CWL - Primary Choice
1^tCK Preamble
2^tCK Preamble
9
N/A
10
N/A
11
N/A
12
14
14
16
16
18
16
18
CWL - Alternate Choice
1^tCK Preamble
2^tCK Preamble
11
N/A
12
N/A
14
N/A
16
16
18
18
20
20
20
20
Note: 1. CWL programmable requirement for MR2[5:3].
When operating in 2^tCK WRITE preamble mode, ^tWTR (command based) and ^tWR
(MR0[11:9]) must be programmed to a value 1 clock greater than the ^tWTR and ^tWR set-
ting normally required for the applicable speed bin to be JEDEC compliant; however,
Micron's DDR4 DRAMs do not require these additional ^tWTR and ^tWR clocks. The
CAS_n-to-CAS_n command delay to either a different bank group (^tCCD_S) or the same
bank group (^tCCD_L) have minimum timing requirements that must be satisfied be-
tween WRITE commands and are stated in the Timing Parameters by Speed Bin tables.
When operating in 2^tCK WRITE preamble mode, ^tCCD_S and ^tCCD_L must also be an
even number of clocks. As an example, if the minimum timing specification requires
only 5^tCK, the 5^tCK has to be rounded up to 6^tCK when operating in 2^tCK WRITE pre-
amble mode, while 5^tCK would be acceptable if operating in 1^tCK WRITE preamble
mode.
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
171
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