RV-8523 Datasheet, PDF (50/57 Pages) MICORO CRYSTAL SWITZERLAND – Real Time Clock

Micro Crystal
Real Time Clock / Calendar Module
RV-8523
15.I²C BUS INTERFACE TIMING
All timing characteristics are valid within the operating supply voltage and ambient temperature range and
reference to 30% and 70% with an input voltage swing of V_SS to V_DD (see figure below).
PARAMETER
SYMBOL
Pin SCL
SCL clock frequency²⁾
LOW period of the SCL clock
HIGH period of the SCL clock
Pin SDA
Data setup time
Data hold time
Pins SCL and SDA
Bus free time between STOP and START condition
Setup time for STOP condition
Hold time (repeated) START condition
Setup time for a repeated START condition
Rise time of both SDA and SCL signals^{3) 4)}
Fall time of both SDA and SCL signals^{3) 4)}
Capacitive load for each bus line
Data valid acknowledge time⁵⁾
Data valid time⁶⁾
Pulse width of spikes that must be suppressed by
the input filter⁷⁾
fSCL
tLOW
tHIGH
tSU;DAT
tHD;DAT
tBUF
tSU;STO
tHD;STA
tSU;STA
tr
tf
Cb
tVD;ACK
tVD;DAT
tSP
STANDARD
MODE
MIN. MAX.
FAST MODE
(FM)
MIN. MAX.
-
100
-
400
4.7
-
1.3
-
4.0
-
0.6
-
250
-
100
-
0
-
0
-
4.7
-
1.3
-
4.0
-
0.6
-
4.0
-
0.6
-
4.7
-
0.6
-
-
1000
20+0.1Cb
300
-
300
20+0.1Cb
300
-
400
-
400
-
3.45
-
0.9
-
3.45
-
0.9
-
50
-
50
FAST MODE
PLUS (FM+)¹⁾
MIN. MAX.
UNIT
-
1000 kHz
0.5
-
µs
0.26
-
µs
50
-
ns
0
-
ns
0.5
-
µs
0.26
-
µs
0.26
-
µs
0.26
-
µs
-
120
ns
-
120
ns
-
550
pF
-
0.45
µs
-
0.45
µs
-
50
ns
1) _{Fast mode plus guaranteed at 3.0 V < VDD < 5.5 V.}
2) _{The minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the SDA or SCL is held}
LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation.
3) _{A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge}
the undefined region of the falling edge of SCL.
4) _{The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows series}
protection resistors to be connected between the SDA pin, the SCL pin and the SDA/SCL bus lines without exceeding the maximum tf.
5) _{tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.}
6) _{tVD;DAT = minimum time for valid SDA output following SCL LOW.}
7) _{Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.}
15.1.TIMING DIAGRAM
Rise and fall times refer to 30% and 70%.
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