RV-8523 Datasheet, PDF (38/57 Pages) MICORO CRYSTAL SWITZERLAND – Real Time Clock

Micro Crystal
Real Time Clock / Calendar Module
RV-8523
At the end of every countdown, the timer sets the countdown timer flag CTBF (register Control 2). CTBF may only
be cleared by using the interface. Instructions, how to clear a flag, are given in section 9.5.
When reading the timer, the current countdown value is returned and not the initial value n. Since it is not possible
to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for
consistent results.
If a new value of n is written before the end of the actual timer-period, this value will take immediate effect. It is not
recommended to change n without first disabling the counter by setting TBC logic 0 (register Timer & CLKOUT).
The update of n is asynchronous to the timer clock. Therefore changing it on the fly could result in a corrupted
value loaded into the countdown counter. This can result in an undetermined countdown period for the first period.
The countdown value n will be correctly stored and correctly loaded on subsequent timer-periods.
Loading the counter with 0 effectively stops the timer.
When starting the countdown timer for the first time, only the first period does not have a fixed duration. The
amount of inaccuracy for the first timer-period depends on the chosen source clock; see section 9.9.1.
When the interrupt generation is enabled (CTBIE = 1) and the countdown timer flag CTAF is set logic 1, interrupt
signals on INT_1 and INT_2 are generated. The interrupt may be generated as a pulsed signal every countdown
period or as a permanently active signal, which follows the condition of CTBF (register Control 2). The TBM bit
(register Timer & CLKOUT) is used to control this mode selection. Interrupt output may be disabled with the CTBIE
bit (register Control 2).
9.9.3.SECOND INTERRUPT TIMER
The RV-8523 has a pre-defined timer, which is used to generate an interrupt once per second. The pulse generator
for the second interrupt timer operates from an internal 64 Hz clock and generates a pulse of ¹â„₆₄ s in duration. It is
independent of the watchdog or countdown timer and can be switched on and off by the SIE bit in register Control 1
(00h).
The interrupt generated by the second interrupt timer may be generated as pulsed signal every second or as a
permanently active signal. The TAM bit (register Timer & CLKOUT) is used to control the interrupt generation
mode.
When the second interrupt timer is enabled (SIE = 1), then the timer sets the flag SF (register Control 2) every
second (see table below). SF may only be cleared by using the interface. Instructions, how to clear a flag, are given
in section 9.5.
Effect of bit SIE on INT_1 and bit SF:
SIE
Result on INT_1
0
No interrupt generated
1
An interrupt once per second
Result on SF
SF never set
SF set when seconds counter increments
When SF is logic 1:
• If TAM (register Timer & CLKOUT) is logic 1, the interrupt is generated as a pulsed signal every second
• If TAM is logic 0, the interrupt is a permanently active signal that remains, until SF is cleared
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