RV-8523 Datasheet, PDF (44/57 Pages) MICORO CRYSTAL SWITZERLAND – Real Time Clock

Micro Crystal
Real Time Clock / Calendar Module
RV-8523
10.3. SYSTEM CONFIGURATION
Since multiple devices can be connected with the I²C bus, all I²C bus devices have a fixed and unique device
number built-in to allow individual addressing of each device.
The device that controls the I²C bus is the Master; the devices which are controlled by the Master are the Slaves. A
device generating a message is a Transmitter; a device receiving a message is the Receiver. The RV-8523 acts as
a Slave-Receiver or Slave-Transmitter.
Before any data is transmitted on the I²C bus, the device which should respond is addressed first. The addressing
is always carried out with the first byte transmitted after the start procedure. The clock signal SCL is only an input
signal, but the data signal SDA is a bidirectional line.
System configuration:
10.4. ACKNOWLEDGE
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is
unlimited. Each byte of 8 bits is followed by an acknowledge cycle.
• A slave receiver, which is addressed, must generate an acknowledge cycle after the reception of each byte
• Also a master receiver must generate an acknowledge cycle after the reception of each byte that has been
clocked out of the slave transmitter
• The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the related acknowledge clock pulse (set-up and
hold times must be considered)
• A master receiver must signal an end of data to the transmitter by not generating an acknowledge cycle on
the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line
HIGH to enable the master to generate a STOP condition
Acknowledgement on the I²C bus is shown on the figure below.
Acknowledgement on the I²C bus:
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