RFPIC12F675K Datasheet, PDF (71/136 Pages) Microchip Technology – 20-Pin FLASH-Based 8-Bit CMOS Microcontroller with UHF ASK/FSK Transmitter

rfPIC12F675
FIGURE 10-12:
CLKOUT
(= FOSC/4)
WATCHDOG TIMER BLOCK DIAGRAM
0
T0CKI
pin
T0SE
1
0
T0CS
1
PSA
8-bit
Prescaler
8
1
SYNC 2
Cycles
0
PSA
Watchdog
Timer
PS0 - PS2
1
WDT
Time-out
0
WDTE
PSA
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
Data Bus
8
TMR0
Set Flag bit T0IF
on Overflow
TABLE 10-9: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Value on
POR, BOD
Value on all
other
RESETS
81h
OPTION_REG GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
2007h Config. bits
CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 uuuu uuuu uuuu uuuu
Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.
10.7 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify. Only the
Least Significant 7 bits of the ID locations are used.
10.8 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note:
The entire data EEPROM and FLASH
program memory will be erased when the
code protection is turned off. The INTOSC
calibration data is also erased. See
rfPIC12F675 Programming Specification
for more information.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 69