RFPIC12F675K Datasheet, PDF (29/136 Pages) Microchip Technology – 20-Pin FLASH-Based 8-Bit CMOS Microcontroller with UHF ASK/FSK Transmitter

4.4 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this Data Sheet. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS2:PS0 bits (OPTION_REG<2:0>).
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
4.4.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
RESET, the following instruction sequence
(Example 4-1) must be executed when changing the
prescaler assignment from Timer0 to WDT.
rfPIC12F675
EXAMPLE 4-1:
CHANGING PRESCALER
(TIMER0→WDT)
bcf
STATUS,RP0
clrwdt
clrf TMR0
bsf
STATUS,RP0
;Bank 0
;Clear WDT
;Clear TMR0 and
; prescaler
;Bank 1
movlw
movwf
clrwdt
movlw
movwf
bcf
b’00101111’ ;Required if desired
OPTION_REG ; PS2:PS0 is
; 000 or 001
;
b’00101xxx’ ;Set postscaler to
OPTION_REG ; desired WDT rate
STATUS,RP0 ;Bank 0
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 4-2. This
precaution must be taken even if the WDT is disabled.
EXAMPLE 4-2:
CHANGING PRESCALER
(WDT→TIMER0)
clrwdt
bsf
STATUS,RP0
;Clear WDT and
; postscaler
;Bank 1
movlw
movwf
bcf
b’xxxx0xxx’ ;Select TMR0,
; prescale, and
; clock source
OPTION_REG ;
STATUS,RP0 ;Bank 0
TABLE 4-1: REGISTERS ASSOCIATED WITH TIMER0
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
Value on
POR, BOD
Value on
all other
RESETS
01h
TMR0
0Bh/8Bh INTCON
Timer0 Module Register
GIE PEIE T0IE
INTE GPIE
T0IF
INTF
GPIF
xxxx xxxx uuuu uuuu
0000 0000 0000 000u
81h
85h
Legend:
OPTION_REG GPPU INTEDG T0CS T0SE PSA
PS2
PS1
PS0 1111 1111
TRISIO
—
— TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111
— = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown.
Shaded cells are not used by the Timer0 module.
1111 1111
--11 1111
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 27