RFPIC12F675K Datasheet, PDF (49/136 Pages) Microchip Technology – 20-Pin FLASH-Based 8-Bit CMOS Microcontroller with UHF ASK/FSK Transmitter

8.3 READING THE EEPROM DATA
MEMORY
To read a data memory location, the user must write
the address to the EEADR register and then set
control bit RD (EECON1<0>), as shown in
Example 8-1. The data is available, in the very next
cycle, in the EEDATA register. Therefore, it can be
read in the next instruction. EEDATA holds this value
until another read, or until it is written to by the user
(during a write operation).
EXAMPLE 8-1: DATA EEPROM READ
bsf
movlw
movwf
bsf
movf
STATUS,RP0
CONFIG_ADDR
EEADR
EECON1,RD
EEDATA,W
;Bank 1
;
;Address to read
;EE Read
;Move data to W
8.4 WRITING TO THE EEPROM DATA
MEMORY
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 8-2.
EXAMPLE 8-2: DATA EEPROM WRITE
bsf STATUS,RP0
bsf EECON1,WREN
bcf INTCON,GIE
movlw 55h
movwf EECON2
movlw AAh
movwf EECON2
bsf EECON1,WR
bsf INTCON,GIE
;Bank 1
;Enable write
;Disable INTs
;Unlock write
;
;
;
;Start the write
;Enable INTS
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
rfPIC12F675
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR<7>) register must be cleared by software.
8.5 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 8-3) to the
desired value to be written.
EXAMPLE 8-3: WRITE VERIFY
bcf
:
bsf
movf
STATUS,RP0
STATUS,RP0
EEDATA,W
bsf EECON1,RD
xorwf
btfss
goto
:
EEDATA,W
STATUS,Z
WRITE_ERR
;Bank 0
;Any code
;Bank 1 READ
;EEDATA not changed
;from previous write
;YES, Read the
;value written
;Is data the same
;No, handle error
;Yes, continue
8.5.1 USING THE DATA EEPROM
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specifications D120 or D120A. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
FLASH program memory.
8.6 PROTECTION AGAINST
SPURIOUS WRITE
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• brown-out
• power glitch
• software malfunction
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 47