PIC16F8X_13 Datasheet, PDF (65/128 Pages) Microchip Technology – 18-pin Flash/EEPROM 8-Bit Microcontrollers

PIC16F8X
NOP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
No Operation
[ label ] NOP
None
No operation
None
00 0000 0xx0 0000
No operation.
1
1
Q1
Q2
Q3
Q4
Decode No-Opera No-Opera No-Operat
tion
tion
ion
Example
NOP
OPTION
Load Option Register
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W)  OPTION
Status Affected: None
Encoding:
00 0000 0110 0010
Description:
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code com-
patibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Words:
1
Cycles:
1
Example
To maintain upward compatibility
with future PIC16CXX products,
do not use this instruction.
RETFIE
Return from Interrupt
Syntax:
[ label ] RETFIE
Operands:
None
Operation:
TOS  PC,
1  GIE
Status Affected: None
Encoding:
00 0000 0000 1001
Description:
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in the
PC. Interrupts are enabled by setting
Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
1st Cycle ^{Decode No-Opera Set the Pop from}
tion
GIE bit the Stack
2nd Cycle
No-Opera No-Opera No-Operat
No-Operat tion
tion
ion
ion
Example
RETFIE
After Interrupt
PC = TOS
GIE = 1
 1996-2013 Microchip Technology Inc.
DS30430D-page 65