PIC16F8X_13 Datasheet, PDF (56/128 Pages) Microchip Technology – 18-pin Flash/EEPROM 8-Bit Microcontrollers

PIC16F8X
TABLE 9-2 PIC16FXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status Notes
MSb
LSb ^Affected
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF f, d
ANDWF f, d
CLRF
f
CLRW -
COMF f, d
DECF
f, d
DECFSZ f, d
INCF
f, d
INCFSZ f, d
IORWF f, d
MOVF f, d
MOVWF f
NOP
-
RLF
f, d
RRF
f, d
SUBWF f, d
SWAPF f, d
XORWF f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1 00
1 00
1 00
1 00
1 00
1 00
1(2) 00
1 00
1(2) 00
1 00
1 00
1 00
1 00
1 00
1 00
1 00
1 00
1 00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f, b
BSF
f, b
BTFSC f, b
BTFSS f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
01 00bb bfff ffff
1,2
1
01 01bb bfff ffff
1,2
1 (2) 01 10bb bfff ffff
3
1 (2) 01 11bb bfff ffff
3
LITERAL AND CONTROL OPERATIONS
ADDLW k
ANDLW k
CALL
k
CLRWDT -
GOTO k
IORLW k
MOVLW k
RETFIE -
RETLW k
RETURN -
SLEEP -
SUBLW k
XORLW k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
1
11 111x kkkk kkkk C,DC,Z
1
11 1001 kkkk kkkk
Z
2
10 0kkk kkkk kkkk
1
00 0000 0110 0100 TO,PD
2
10 1kkk kkkk kkkk
1
11 1000 kkkk kkkk
Z
1
11 00xx kkkk kkkk
2
00 0000 0000 1001
2
11 01xx kkkk kkkk
2
00 0000 0000 1000
1
00 0000 0110 0011 TO,PD
1
11 110x kkkk kkkk C,DC,Z
1
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS30430D-page 56
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