MRF49XA Datasheet, PDF (57/102 Pages) Microchip Technology – ISM Band Sub-GHz RF Transceiver

MRF49XA
FIGURE 3-9:
FSK MODULATED DEVIATION – MAXIMUM TX TO RX OFFSET
10 kHz + Data Rate
2 x deviation
Amplitude
Baseband Filter Characteristic
Data Rate
TX-RX Offset
BBBW
Programmable
10 kHz
The baseband filtering type can also be selected
between an analog filter and a digital filter.
3.10.1 ANALOG FILTERING MODE
For analog filtering, a simple RC low-pass filter is used,
along with a Schmitt Trigger circuit. The demodulator
output is fed to the RCLKOUT/FCAP/FINT pin over a
10 kΩ resistor. The filter cut-off frequency is set by the
external capacitor connected to this pin and VSS. A
10 kΩ resistor and the Schmitt Trigger are integrated
on the chip. An external capacitor for the RC filter has
to be chosen in accordance with the required bit rate.
The receiver can handle up to 256 kbps of data rate in
analog operation. The receive data rate is program-
mable from 337 bps to 256 kbps. An internal prescaler
can be used to give better resolution when setting up
the receive data rate. The prescaler is optional and can
be disabled through DRSREG. The analog filtering
does not use the FIFO and the clock. The clock is not
provided for the demodulated data, and hence, there is
no need for setting the correct bit rate.
RX Center TX Center
Freq.
Freq.
Frequency
3.10.2 DIGITAL FILTERING MODE
A digital filter is used with a clock frequency at 29 times
the data rate. For digital filtering, the synchronized
clock to the data is provided by the clock recovery
circuit. By using this clock, the received data can fill the
FIFO. If the FIFO is not used, the recovered clock can
be accessed through RCLKOUT/FCAP/ FINT pin.
The clock recovery circuit operates in three modes:
Automatic mode, Slow mode and Fast mode. All three
modes are configurable through BBFCREG. Each
mode is dependent on the type of signals it uses to
determine the valid data and also the number of incom-
ing preamble bits present at the beginning of the
packet. In Automatic mode, the CR clock recovery
circuit automatically switches between the Fast and
Slow mode. The noise immunity of the clock recovery
circuit is very high in Slow mode; however, it has slower
settling time and requires more accurate data timing
than in Fast mode.
The registers associated with baseband filtering are:
• STSREG (see Register 2-1)
• RXCREG (see Register 2-7)
• BBFCREG (see Register 2-8)
• PMCREG (see Register 2-13)
© 2009 Microchip Technology Inc.
Preliminary
DS70590B-page 55